Defect And Dislocati On Suppression Due To Lattice Mismatch, E.g., Lattice Adaptation (epo) Patents (Class 257/E21.125)
  • Patent number: 10109756
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu
  • Patent number: 10002979
    Abstract: Disclosed are a semiconductor photodiode (PD) or phototransistor (PT) photo detector with a unipolarly doped edge region containing a portion of the photon absorption layer and occupying over 99% of the photo detector area as projected on a plane parallel to the semiconductor substrate. Embodiments also relate to methods of making the photo detector.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 19, 2018
    Assignee: WAVEFRONT HOLDINGS, LLC
    Inventor: Jie Yao
  • Patent number: 9905730
    Abstract: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 27, 2018
    Assignee: Lumileds LLC
    Inventors: Patrick N. Grillot, Rafael I. Aldaz, Deborah L. Colbentz, Anneli Munkholm, Hanmin Zhao
  • Patent number: 9741874
    Abstract: A scalable voltage source having a number N of partial voltage sources implemented as semiconductor diodes connected to one another in series, wherein each of the partial voltage sources has a semiconductor diode with a p-n junction. A tunnel diode is formed between sequential pairs of partial voltage sources, wherein the tunnel diode has multiple semiconductor layers with a larger band gap than the band gap of the p/n absorption layers and the semiconductor layers with the larger band gap are each made of a material with modified stoichiometry and/or a different elemental composition than the p/n absorption layers of the semiconductor diode. The partial voltage sources and the tunnel diodes are monolithically integrated together, and jointly form a first stack with a top and a bottom, and the number N of partial voltage sources is greater than or equal to two.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: August 22, 2017
    Assignee: Azur Space Solar Power GmbH
    Inventors: Daniel Fuhrmann, Victor Khorenko, Wolfgang Guter
  • Patent number: 9583571
    Abstract: A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×105 cm?2. Thus, a silicon carbide semiconductor substrate enabling improved yield of semiconductor devices can be provided.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taro Nishiguchi, Shin Harada, Shinsuke Fujiwara
  • Patent number: 9540227
    Abstract: A microelectromechanical systems (MEMS) device includes a structural layer having a top surface. The top surface includes surface regions that are generally parallel to one another but are offset relative to one another such that a stress concentration location is formed between them. Laterally propagating shallow surface cracks have a tendency to form in the structural layer, especially near the joints between the surface regions. A method entails fabricating the MEMS device and forming trenchesin the top surface of the structural layer of the MEMS device. The trenches act as a crack inhibition feature to largely prevent the formation of deep cracks in structural layer which might otherwise result in MEMS device failure.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 10, 2017
    Assignee: NXP USA, Inc.
    Inventor: Chad S. Dawson
  • Patent number: 9515196
    Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Eugene A. Fitzgerald
  • Patent number: 9450054
    Abstract: A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×105 cm?2. Thus, a silicon carbide semiconductor substrate enabling improved yield of semiconductor devices can be provided.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: September 20, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Taro Nishiguchi, Shin Harada, Shinsuke Fujiwara
  • Patent number: 9419110
    Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: August 16, 2016
    Assignee: IMEC VZW
    Inventors: Clement Merckling, Nadine Collaert
  • Patent number: 9012936
    Abstract: The sapphire substrate has a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device and comprising a plurality of projections of the principal surface, wherein an outer periphery of a bottom surface of each of the projections has at least one depression. This depression is in the horizontal direction. The plurality of projections are arranged so that a straight line passes through the inside of at least any one of projections when the straight line is drawn at any position in any direction in a plane including the bottom surfaces of the plurality of projections.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: April 21, 2015
    Assignee: Nichia Corporation
    Inventors: Junya Narita, Takuya Okada, Yohei Wakai, Yoshiki Inoue, Naoya Sako, Katsuyoshi Kadan
  • Patent number: 8987028
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Patent number: 8981208
    Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell includes a substrate of a first conductive type, an emitter layer of a second conductive type opposite the first conductive type, a plurality of first electrodes connected to the emitter layer, at least one first current collector connected to the plurality of first electrodes, and a second electrode connected to the substrate. The emitter layer forms a p-n junction along with the substrate. Each of the plurality of first electrodes has a multi-layered structure, and the at least one first current collector has a single-layered structure.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: March 17, 2015
    Assignee: LG Electronics Inc.
    Inventors: Sungjin Kim, Gyeayoung Kwag, Younggu Do, Mann Yi, Seongeun Lee, Youngsung Yang, Taeyoung Kwon, Haejong Cho, Minho Choi, Juhwa Cheong
  • Patent number: 8906487
    Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 8883609
    Abstract: According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8847262
    Abstract: A sapphire substrate having a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device comprises a plurality of projections on the principal surface. Each of the projections has a bottom that has a substantially polygonal shape. Each side of the bottom of the projections has a depression in its center. Vertexes of the bottoms of the respective projections extend in a direction that is within a range of ±10 degrees of a direction that is rotated counter-clockwise by 30 degrees from a crystal axis “a” of the sapphire substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Nichia Corporation
    Inventors: Junya Narita, Takuya Okada, Yohei Wakai, Yoshiki Inoue, Naoya Sako, Katsuyoshi Kadan
  • Patent number: 8823025
    Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8823056
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christopher Leitz, Christopher J. Vineis, Richard Westhoff, Vicky Yang, Matthew T. Currie
  • Patent number: 8823027
    Abstract: A light emitting device having a relatively simple configuration is provided that emits stable light having a plurality of wavelengths. The light emitting device 1 comprises, in sequence, a composite substrate 3 and a gallium nitride-based semiconductor layer 5 including a light emitting layer 9. The composite substrate 3 includes a base 19 and a gallium nitride layer, the gallium nitride-based semiconductor layer 5 being disposed on a principal surface of the gallium nitride layer, the angle ? defined by the c-axis of the gallium nitride layer and a normal line N1 to the principal surface S1 of the gallium nitride layer ranging from 50 to 130 degrees, the light emitting layer 9 emitting light with an absolute value of the degree of polarization of 0.2 or more, the base 19 containing a fluorescent material that emits a fluorescent light component induced by irradiation of a light component emitted from the light emitting layer 9.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: September 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takashi Kyono
  • Patent number: 8785907
    Abstract: An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: Niti Goel, Niloy Mukherjee, Seung Hoon Sung, Van H. Le, Matthew V. Metz, Jack T. Kavalieros, Ravi Pillarisetty, Sanaz K. Gardner, Sansaptak Dasgupta, Willy Rachmady, Benjamin Chu-Kung, Marko Radosavljevic, Gilbert Dewey, Marc C. French, Jessica Kachian, Satyarth Suri, Robert S. Chau
  • Patent number: 8772757
    Abstract: Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 360 nm with wall plug efficiencies of at least than 4% are provided. Wall plug efficiencies may be at least 5% or at least 6%. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 345 nm with wall plug efficiencies of at least than 2% are also provided. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 330 nm with wall plug efficiencies of at least than 0.4% are provided. Light emitting devices and methods of fabricating light emitting devices having a peak output wavelength of not greater than 360 nm and an output power of at least 5 mW, having a peak output wavelength of 345 nm or less and an output power of at least 3 mW and/or a peak output wavelength of 330 nm or less and an output power of at least 0.3 mW at a current density of less than about 0.35 ?A/?m2 are also provided.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: July 8, 2014
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, Michael John Bergmann, Amber Abare, Kevin Haberern
  • Patent number: 8754419
    Abstract: A semiconductor device includes a Si substrate having a principal plane that is a crystal surface inclined at an off angle of 0.1 degrees or less with respect to a (111) plane, an AlN layer that is provided so as to contact the principal plane of the Si substrate and is configured so that an FWHM of a rocking curve of a (002) plane by x-ray diffraction is not greater than 2000 seconds, and a GaN-based semiconductor layer formed on the AlN layer.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 17, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken Nakata, Isao Makabe, Keiichi Yui, Takamitsu Kitamura
  • Patent number: 8697466
    Abstract: A method of manufacturing a nitride semiconductor device includes the step of forming a second nitride semiconductor layer having an inclined facet by metal-organic chemical vapor deposition, in which a molar flow ratio of a group V element gas to a group III element gas that are supplied to a growth chamber of a metal-organic chemical vapor deposition growth apparatus is set at 240 or less.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Komada
  • Patent number: 8664084
    Abstract: A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: March 4, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Chrystel Deguet, Laurent Clavelier
  • Patent number: 8652918
    Abstract: A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 18, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Andre Strittmatter
  • Patent number: 8629045
    Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Zhiyuan Cheng
  • Patent number: 8618639
    Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8580593
    Abstract: Epitaxial formation structures and associated methods of manufacturing solid state lighting (“SSL”) devices with target thermal expansion characteristics are disclosed herein. In one embodiment, an SSL device includes a composite structure having a composite CTE temperature dependency, a formation structure on the composite structure, and an SSL structure on the formation structure. The SSL structure has an SSL temperature dependency, and a difference between the composite CTE and SSL temperature dependencies is below 3 ppm/° C. over the temperature range.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Thomas Pinnington
  • Patent number: 8545627
    Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 1, 2013
    Assignee: Arizona Board of Regents
    Inventors: John Kouvetakis, Radek Roucka
  • Patent number: 8541794
    Abstract: A nitride semiconductor device including a light emitting device comprises a n-type region of one or more nitride semiconductor layers having n-type conductivity, a p-type region of one or more nitride semiconductor layers having p-type conductivity and an active layer between the n-type region and the p-type region. In such devices, there is provided with a super lattice layer comprising first layers and second layers which are nitride semiconductors having a different composition respectively. The super lattice structure makes working current and voltage of the device lowered, resulting in realization of more efficient devices.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: September 24, 2013
    Assignee: Nichia Chemical Industries, Ltd.
    Inventors: Shinichi Nagahama, Masayuki Senoh, Shuji Nakamura
  • Patent number: 8465997
    Abstract: A manufacturing method of a group III nitride semiconductor comprising: preparing a substrate including a buffer layer; forming a first layer on the buffer layer from a group III nitride semiconductor by MOCVD while doping an anti-surfactant, wherein a thickness of the first layer is equal to or thinner than 2 ?m; forming a second layer on the first layer from a group III nitride semiconductor by MOCVD while doping at least one of surfactant and an anti-surfactant; and controlling a crystalline quality and a surface flatness of the second layer by adjusting an amount of the anti-surfactant and the surfactant doped during the formation of the second layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 18, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Koji Okuno
  • Patent number: 8410523
    Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: April 2, 2013
    Inventors: Diana L. Huffaker, Larry R. Dawson, Ganesh Balakrishnan
  • Patent number: 8349711
    Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: January 8, 2013
    Assignee: Kyma Technologies, Inc.
    Inventors: Edward A. Preble, Lianghong Liu, Andrew D. Hanser, N. Mark Williams, Xueping Xu
  • Patent number: 8310028
    Abstract: A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: November 13, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Kiriyama, Noriaki Kawamoto
  • Patent number: 8304276
    Abstract: An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: November 6, 2012
    Assignee: Alcatel Lucent
    Inventor: George Patrick Watson
  • Patent number: 8298840
    Abstract: Thin freestanding nitride films are used as a growth substrate to enhance the optical, electrical, mechanical and mobility of nitride based devices and to enable the use of thick transparent conductive oxides. Optoelectronic devices such as LEDs, laser diodes, solar cells, biomedical devices, thermoelectrics, and other optoelectronic devices may be fabricated on the freestanding nitride films. The refractive index of the freestanding nitride films can be controlled via alloy composition. Light guiding or light extraction optical elements may be formed based on freestanding nitride films with or without layers. Dual sided processing is enabled by use of these freestanding nitride films. This enables more efficient output for light emitting devices and more efficient energy conversion for solar cells.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: October 30, 2012
    Assignee: Goldeneye, Inc.
    Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
  • Patent number: 8274097
    Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Zhiyuan Cheng
  • Patent number: 8212287
    Abstract: A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides sign0ificant blocking of both vertically and diagonally running defects during growth.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 3, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Andre Strittmatter
  • Patent number: 8198681
    Abstract: The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Infineon Technologies AG
    Inventor: Georg Tempel
  • Patent number: 8178951
    Abstract: There is provided a compound semiconductor substrate prepared by forming a point defect in an inside structure thereof by implanting an electrically-neutral impurity with energy of 0.1 to 10 MeV on a surface of the substrate. When the compound semiconductor is undoped, electrical resistance increases to increase insulating properties, and when the compound semiconductor is doped with an n-type dopant, the impurity is implanted and charge concentration of the substrate increases to increase conductive properties. In accordance with the present invention, the various electrical properties needed for the compound semiconductor can be effectively controlled by increasing the insulating properties of the undoped compound semiconductor or by increasing the charge concentration of the n-type compound semiconductor, and the application range to various devices can be expanded.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: May 15, 2012
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: Young Zo Yoo, Hyun Min Shin, Jun Sung Choi
  • Patent number: 8173991
    Abstract: An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 8, 2012
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Stauss, Matthias Peter, Alexander Walter
  • Patent number: 8173469
    Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 8, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kyung Wook Park, Myung Hoon Jung
  • Patent number: 8154022
    Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 10, 2012
    Assignee: Soitec
    Inventors: Chantal Arena, Fabrice Letertre
  • Patent number: 8148241
    Abstract: One embodiment of depositing a gallium nitride (GaN) film on a substrate comprises providing a source of indium (In) and gallium (Ga) and depositing a monolayer of indium (In) on the surface of the gallium nitride (GaN) film. The monolayer of indium (In) acts as a surfactant to modify the surface energy and facilitate the epitaxial growth of the film by suppressing three dimensional growth and enhancing or facilitating two dimensional growth. The deposition temperature is kept sufficiently high to enable the indium (In) to undergo absorption and desorption on the gallium nitride (GaN) film without being incorporated into the solid phase gallium nitride (GaN) film. The gallium (Ga) and indium (In) can be provided by a single source or separate sources.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 3, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Olga Kryliouk
  • Patent number: 8138495
    Abstract: An apparatus comprising a microelectromechanical system. The microelectromechanical system includes a crystalline structural element having dislocations therein. For at least about 60 percent of adjacent pairs of the dislocations, direction vectors of the dislocations form acute angles of less than about 45 degrees.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: March 20, 2012
    Assignee: Alcatel Lucent
    Inventor: George Patrick Watson
  • Patent number: 8129747
    Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 6, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Richard Westhoff, Vicky Yang, Matthew T. Currie, Christopher J. Vineis, Christopher Leitz
  • Patent number: 8093625
    Abstract: Disclosed is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises a buffer layer having a super-lattice layer on a silicon substrate, a first conductive clad layer on the buffer layer, an active layer on the first conductive clad layer, and a second conductive clad layer on the active layer.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: January 10, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sang Kyun Shim
  • Patent number: 8063397
    Abstract: Semiconductor light-emitting structures are shown on engineered substrates having a graded composition. The composition of the substrate may be graded to achieve a lattice constant on which a yellow-green light-emitting semiconductor material may be disposed. In some embodiments, the structure may be substantially free of aluminum.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 22, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael J. Mori, Eugene A. Fitzgerald
  • Patent number: 8058090
    Abstract: The present invention relates to the field of thin film solar cells and particularly to an apparatus and method for manufacturing thin film solar cells. At least one material is deposited onto a substrate, whereby the deposited material is heated by means of heating means on a limited area of the deposited material. The substrate and the heating means are continuously moved in relation to each other until a predetermined area of the deposited material is heated, whereby the heated material is cooled in a controlled way, thus, obtaining a desired crystalline structure of the deposited material.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: November 15, 2011
    Assignee: Midsummer AB
    Inventor: Sven Lindström
  • Patent number: 8039291
    Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; attaching a surrogate second substrate over the third solar subcell and removing the first substrate; and etching a first trough around the periphery of the solar cell to the surrogate second substrate so as to form a mesa structure on the surrogate second substrate and facilitate the removal of the solar cell from the surrogate second substrate.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 18, 2011
    Assignee: Emcore Solar Power, Inc.
    Inventors: Arthur Cornfeld, Tansen Varghese, Jacqueline Diaz
  • Patent number: 8039901
    Abstract: A semiconductor device includes a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: October 18, 2011
    Assignee: Sony Corporation
    Inventor: Takuji Matsumoto