Defect And Dislocati On Suppression Due To Lattice Mismatch, E.g., Lattice Adaptation (epo) Patents (Class 257/E21.125)
-
Patent number: 8017415Abstract: Thin freestanding nitride films are used as a growth substrate to enhance the optical, electrical, mechanical and mobility of nitride based devices and to enable the use of thick transparent conductive oxides. Optoelectronic devices such as LEDs, laser diodes, solar cells, biomedical devices, thermoelectrics, and other optoelectronic devices may be fabricated on the freestanding nitride films. The refractive index of the freestanding nitride films can be controlled via alloy composition. Light guiding or light extraction optical elements may be formed based on freestanding nitride films with or without layers. Dual sided processing is enabled by use of these freestanding nitride films. This enables more efficient output for light emitting devices and more efficient energy conversion for solar cells.Type: GrantFiled: November 4, 2009Date of Patent: September 13, 2011Assignee: Goldeneye, Inc.Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
-
Patent number: 7943494Abstract: The present invention provides a method for blocking the dislocation propagation of a semiconductor. A semiconductor layer is formed by epitaxial process on a substrate. A plurality of recesses is formed on the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. Thereafter, a blocking layer is formed on each of the plurality of recesses. The aforesaid semiconductor layer undergoes epitaxial process again on the aforesaid semiconductor layer, and laterally overgrows to redirect the dislocation defects.Type: GrantFiled: October 15, 2009Date of Patent: May 17, 2011Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Peng Yi Wu, Shih Cheng Huang, Po Min Tu, Ying Chao Yeh, Wen Yu Lin, Shih Hsiung Chan
-
Patent number: 7923273Abstract: An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible with the PCB.Type: GrantFiled: July 31, 2007Date of Patent: April 12, 2011Assignee: Banpil Photonics, Inc.Inventor: Achyut Kumar Dutta
-
Patent number: 7915636Abstract: The present disclosure relates to a III-nitride semiconductor light emitting device which improves external quantum efficiency by using a p-type nitride semiconductor layer with a rough surface, the p-type nitride semiconductor layer including: a first nitride semiconductor layer with a first doping concentration, a second nitride semiconductor layer with a second doping concentration lower than the first doping concentration and with the rough surface, and a third nitride semiconductor layer with a higher doping concentration than a second doping concentration.Type: GrantFiled: August 21, 2008Date of Patent: March 29, 2011Assignee: Epivalley Co., Ltd.Inventor: Chang Myung Lee
-
Patent number: 7868335Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.Type: GrantFiled: August 18, 2008Date of Patent: January 11, 2011Assignee: HRL Laboratories, LLCInventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
-
Patent number: 7858450Abstract: An optic mask for crystallizing amorphous silicon comprises a first slit region including a plurality of slits regularly arranged for defining incident region of laser beam, wherein the slits of the first slit region are formed to slope by a predetermined angle to the direction of transfer of the optic mask in crystallization process, and wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.Type: GrantFiled: January 5, 2005Date of Patent: December 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Jin Chung, Myung-Koo Kang, Jae-Bok Lee
-
Patent number: 7858424Abstract: A method for producing a sensor array including a monolithically integrated circuit is described as well as a sensor array. This sensor array has a micromechanical sensor structure, in which a first partial structure which is associated with the sensor structure is produced at the same time as a second partial structure which is associated with the circuit, a process variation of the first partial structure being performed in order to adjust a structure property of the sensor structure while the second partial structure remains the same.Type: GrantFiled: September 25, 2006Date of Patent: December 28, 2010Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Simon Armbruster
-
Patent number: 7829442Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: November 16, 2007Date of Patent: November 9, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Richard Westhoff, Vicky K. Yang, Matthew T. Currie, Christopher Vineis, Christopher Leitz
-
Patent number: 7812374Abstract: A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.Type: GrantFiled: June 27, 2007Date of Patent: October 12, 2010Assignee: Panasonic CorporationInventors: Nobuyuki Tamura, Ken Suzuki, Katsuhiro Ootani
-
Patent number: 7812340Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.Type: GrantFiled: June 13, 2003Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Guy Moshe Cohen, Patricia May Mooney
-
Patent number: 7790489Abstract: A III-V group nitride system semiconductor self-standing substrate has: a first III-V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a second III-V group nitride system semiconductor crystal layer that is formed up to 10 ?m from the surface of the substrate on the first III-V group nitride system semiconductor crystal layer and that has a dislocation density distribution that is substantially uniform.Type: GrantFiled: April 23, 2007Date of Patent: September 7, 2010Assignee: Hitachi Cable, Ltd.Inventor: Masatomo Shibata
-
Patent number: 7790563Abstract: A semiconductor device of the present invention is manufactured by the following steps: forming a single-crystal semiconductor layer over a substrate having an insulating surface; irradiating a region of the single-crystal semiconductor layer with laser light; forming a circuit of a pixel portion using a region of the single-crystal semiconductor layer which is not irradiated with the laser light; and forming a driver circuit for driving the circuit of the pixel portion using the region of the single-crystal semiconductor layer which is irradiated with the laser light. Thus, a semiconductor device using a single-crystal semiconductor layer which is suitable for a peripheral driver circuit region and a single-crystal semiconductor layer which is suitable for a pixel region can be provided.Type: GrantFiled: July 8, 2008Date of Patent: September 7, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tetsuya Kakehata
-
Patent number: 7741146Abstract: A method of forming a multifunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; attaching a surrogate second substrate over the third solar subcell and removing the first substrate; and etching a first trough around the periphery of the solar cell to the surrogate second substrate so as to form a mesa structure on the surrogate second substrate and facilitate the removal of said soType: GrantFiled: August 12, 2008Date of Patent: June 22, 2010Assignee: Emcore Solar Power, Inc.Inventors: Arthur Cornfeld, Tansen Varghese, Jacqueline Diaz
-
Patent number: 7696071Abstract: The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B). Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.Type: GrantFiled: October 24, 2007Date of Patent: April 13, 2010Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki KaishaInventors: Masahito Kodama, Eiko Hayashi, Masahiro Sugimoto
-
Patent number: 7670928Abstract: A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.Type: GrantFiled: June 14, 2006Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Mohamad A. Shaheen, Willy Rachmady, Peter Tolchinsky
-
Patent number: 7615420Abstract: The method for manufacturing the indium gallium aluminium nitride (InGaAlN) thin film on silicon substrate, which comprises the following steps: introducing magnesium metal for processing online region mask film, that is, or forming one magnesium mask film layer or metal transition layer; then forming one metal transition layer or magnesium mask layer, finally forming one layer of indium gallium aluminium nitride semiconductor layer; or firstly forming one layer of metal transition layer on silicon substrate and then forming the first indium gallium aluminium nitride semiconductor layer, magnesium mask layer and second indium gallium aluminium nitride semiconductor layer in this order. This invention can reduce the dislocation density of indium gallium aluminium nitride materials and improve crystal quality.Type: GrantFiled: September 26, 2006Date of Patent: November 10, 2009Assignee: Lattice Power (Jiangxi) CorporationInventors: Fengyi Jiang, Li Wang, Wenqing Fang
-
Patent number: 7566940Abstract: Embodiments of MEMS devices comprise a conductive movable layer spaced apart from a conductive fixed layer by a gap, and supported by rigid support structures, or rivets, overlying depressions in the conductive movable layer, or by posts underlying depressions in the conductive movable layer. In certain embodiments, portions of the rivet structures extend through the movable layer and contact underlying layers. In other embodiments, the material used to form the rigid support structures may also be used to passivate otherwise exposed electrical leads in electrical connection with the MEMS devices, protecting the electrical leads from damage or other interference.Type: GrantFiled: July 21, 2006Date of Patent: July 28, 2009Assignee: QUALCOMM MEMS Technologies, Inc.Inventors: Teruo Sasagawa, SuryaPrakash Ganti, Mark W. Miles, Clarence Chui, Manish Kothari, Ming-Hau Tung
-
Publication number: 20080315255Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Inventors: Jer-Shen Maa, Tingkai Li, Douglas J. Tweet, Gregory M. Stecker, Sheng Teng Hsu
-
Patent number: 7459718Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.Type: GrantFiled: March 22, 2006Date of Patent: December 2, 2008Assignee: Nichia CorporationInventors: Mitsuo Hayamura, Shiro Akamatsu
-
Patent number: 7396747Abstract: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.Type: GrantFiled: August 16, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Juan Cai, Kevin K. Chan, Patricia M. Mooney, Kern Rim
-
Patent number: 7375385Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: August 22, 2003Date of Patent: May 20, 2008Assignee: AmberWave Systems CorporationInventors: Richard Westhoff, Vicky Yang, Matthew Currie, Christopher Vineis, Christopher Leitz
-
Patent number: 7368310Abstract: In a method of making a semiconductor light generating device, a GaN-based semiconductor portion is formed on a GaN or AlGaN substrate. The GaN-based semiconductor portion includes a light generating film. An electrode film is formed on the GaN-based semiconductor film. A conductive substrate is bonded to a surface of the electrode film using a conductive adhesive. After bonding the conductive substrate, the GaN or AlGaN substrate is separated from the GaN-based semiconductor portion to form the semiconductor light generating device.Type: GrantFiled: August 5, 2004Date of Patent: May 6, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventor: Katsushi Akita
-
Publication number: 20080070397Abstract: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.Type: ApplicationFiled: November 26, 2007Publication date: March 20, 2008Inventors: Anthony Lochtefeld, Christopher Leitz, Matthew Currie, Mayank Bulsara
-
Patent number: 7342261Abstract: A light emitting device includes a substrate having a patterned surface and formed with a plurality of spaced apart cavities, and an epitaxial layer formed on the patterned surface of the substrate, having a patterned surface that is in face-to-face contact with the patterned surface of the substrate, and formed with a plurality of protrusions that protrude from the patterned surface of the epitaxial layer and that are respectively received in the cavities. Each of the protrusions is polygonal in shape and defines a plurality of vertices. The vertices of each of the protrusions contact the cavity-defining wall of the respective one of the cavities so as to form a plurality of closed pores between each of the protrusions and the cavity-defining wall of the respective one of the cavities.Type: GrantFiled: May 16, 2005Date of Patent: March 11, 2008Inventors: Dong-Sing Wuu, Ray-Hua Horng, Woei-Kai Wang
-
Patent number: 7262485Abstract: A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substrate for growing an electro-optical single crystal thin film which can obtain an electro-optical single crystal thin film of BTO single crystal thin film 6 etc. with a large size and a very high quality.Type: GrantFiled: July 6, 2005Date of Patent: August 28, 2007Assignee: Covalent Materials CorporationInventors: Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi, Jun Komiyama
-
Patent number: 7202102Abstract: A photodiode with a semiconductor intrinsic light absorption layer has at least one p-doped light absorption layer or an n-doped light absorption layer, and preferably both. The diode also has a cathode electrode and an anode electrode electrically coupled with the p-doped light absorption layer or the n-doped light absorption layer.Type: GrantFiled: December 16, 2003Date of Patent: April 10, 2007Assignee: JDS Uniphase CorporationInventor: Jie Yao
-
Patent number: 7202512Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.Type: GrantFiled: August 11, 2004Date of Patent: April 10, 2007Assignee: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Sheng-Wei Lee, Kao-Feng Liao, Lih-Juann Chen, Chee-Wee Liu
-
Patent number: 7186580Abstract: Systems and methods are disclosed for fabricating a semiconductor light emitting diode (LED) device by forming an n-gallium nitride (n-GaN) layer on the LED device; and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.Type: GrantFiled: January 11, 2005Date of Patent: March 6, 2007Assignee: Semileds CorporationInventors: Chuong Anh Tran, Trung Tri Doan
-
Patent number: 7081410Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.Type: GrantFiled: April 16, 2004Date of Patent: July 25, 2006Assignee: Massachusetts Institute of TechnologyInventor: Eugene A. Fitzgerald