Abstract: A method of manufacturing an LED of high reflectivity includes forming a substrate; depositing an n-type GaN layer on the substrate; depositing an active layer on a first portion of the n-type GaN layer; attaching an n-type metal electrode to a second portion of the n-type GaN layer; depositing a p-type GaN layer on the active layer; forming a metal reflector on the p-type GaN layer; attaching a p-type metal electrode to the metal reflector; and attaching the p-type metal electrode and the n-type metal electrode to an epitaxial layer respectively. The metal reflector includes a transparent layer, an Ag layer, and an Au layer. The transparent layer and the Ag layer are formed by annealing in a furnace, and the Au layer is subsequently coated on the Ag layer.

Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.

Abstract: A laminated structure having light-emitting units is formed on a single-crystal wafer. Electrode patterns are formed on the single-crystal wafer opposite the light-emitting units. Dummy patterns are formed on the single-crystal wafer at a location spaced apart from a location opposite the light-emitting units, and offset from a desired cleavage line intersecting the light-emitting units. A scratch is formed on the desired cleavage line. The wafer is cleaved, originating on the scratch, along the cleavage line orientation, in the direction from the dummy pattern, toward the light-emitting units.

Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.

Abstract: A semiconductor laser device includes an n-type cladding layer 103 made of n?type (Al0.3Ga0.7)0.5In0.5P, an undoped active layer 104 and a first p-type cladding layer 105 made of p?type (Al0.3Ga0.7)0.5In0.5P. These layers are successively stacked in bottom-to-top order. The active layer 104 has a multi-quantum well structure composed of a first optical guide layer of undoped Al0.4Ga0.6As, a layered structure in which well layers of undoped GaAs and barrier layers of undoped Al0.4Ga0.6As are alternately formed, and a second optical guide layer of undoped Al0.4Ga0.6As. The first optical guide layer, the layered structure and the second optical guide layer are successively stacked in bottom-to-top order.

Abstract: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn1-X-YO2, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Abstract: Methods and systems are provided of fabricating a compound nitride semiconductor structure. A substrate is disposed within a processing chamber into which a group-III precursor and a nitrogen precursor are flowed. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process using the precursors. The substrate is transferred to a transfer chamber where a temperature and a curvature of the layer are measured. The substrate is then transferred to a second processing chamber where a second layer is deposited.

Abstract: A nitride semiconductor light emitting device comprising an n-side nitride semiconductor layer and a p-side nitride semiconductor layer formed on a substrate, with a light transmitting electrode 10 formed on the p-side nitride semiconductor layer, and the p-side pad electrode 14 formed for the connection with an outside circuit, and the n-side pad electrode 12 formed on the n-side nitride semiconductor layer for the connection with the outside circuit, so as to extract light on the p-side nitride semiconductor layer side, wherein taper angles of end faces of the light transmitting electrode 10 and/or the p-side nitride semiconductor layer are made different depending on the position.

Abstract: A method of producing nitride based heterostructure devices by using a quaternary layer comprised of AlInGaN. The quaternary layer may be used in conjunction with a ternary layer in varying thicknesses and compositions that independently adjust polarization charges and band offsets for device structure optimization by using strain compensation profiles. The profiles can be adjusted by altering profiles of molar fractions of In and Al.

Abstract: A light emitting device includes a substrate having a patterned surface and formed with a plurality of spaced apart cavities, and an epitaxial layer formed on the patterned surface of the substrate, having a patterned surface that is in face-to-face contact with the patterned surface of the substrate, and formed with a plurality of protrusions that protrude from the patterned surface of the epitaxial layer and that are respectively received in the cavities. Each of the protrusions is polygonal in shape and defines a plurality of vertices. The vertices of each of the protrusions contact the cavity-defining wall of the respective one of the cavities so as to form a plurality of closed pores between each of the protrusions and the cavity-defining wall of the respective one of the cavities.

Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1?100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11?20> direction lying in a range of 0.00 degree to 0.06 degree.

Abstract: Large area, uniformly low dislocation density single crystal Ill-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm?2, and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the Ill-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract: A single step process for nucleation and subsequent epitaxial growth on a lattice mismatched substrate is achieved by pre-treating the substrate surface with at least one group III reactant or at least one group II reactant prior to the introduction of a group V reactant or a group VI reactant. The group III reactant or the group II reactant is introduced into a growth chamber at an elevated growth temperature to wet a substrate surface prior to any actual crystal growth. Once the pre-treatment of the surface is complete, a group V reactant or a group VI reactant is introduced to the growth chamber to commence the deposition of a nucleation layer. A buffer layer is then grown on the nucleation layer providing a surface upon which the epitaxial layer is grown preferably without changing the temperature within the chamber.

Abstract: The liquid discharge head has a three-dimensional structure which defines a space including a pressure chamber filled with liquid and a flow channel for supplying the liquid to the pressure chamber, the three-dimensional structure being formed by depositing a composition material on a substrate according to a deposition method, and a drive element which causes discharge of the liquid from the pressure chamber through a nozzle.

Abstract: A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon layer; depositing a dielectric layer on the wafer to cover a gate module of the IC device; smoothing the dielectric; implanting ions to form a defect layer; cutting the wafer into individual silicon dies; preparing a glass panel and the silicon dies for bonding; bonding the silicon dies onto the glass panel to form a bonded structure; annealing the bonded structure; splitting the bonded structure along the defect layer; removing the remaining silicon layer from the silicon substrate and relaxed SiGe layer on the silicon die on the glass panel; and completing the glass panel circuitry.

Abstract: A method of fabricating a compound semiconductor layer has steps of forming a first layer made of an oxidizable material on a substrate, forming a second layer made of a compound semiconductor on the first layer, oxidizing the first layer made of the oxidizable material to an oxide layer and forming a third layer made of compound semiconductor that constitutes a semiconductor element on the second layer.