Applied Layer Is Oxide, E.g., P 2 O 5 , Psg, H 3 Bo 3 , Doped Oxide (epo) Patents (Class 257/E21.149)
  • Patent number: 10535769
    Abstract: A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 14, 2020
    Assignee: SONY CORPORATION
    Inventors: Satoru Mayuzumi, Hitoshi Wakabayashi
  • Patent number: 10410872
    Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Ziqing Duan, Milind Gadre, Praket P. Jha, Abhijit Basu Mallick, Deenesh Padhi
  • Patent number: 10317710
    Abstract: A novel phase shifter design for carrier depletion based silicon modulators, based on an experimentally validated model, is described. It is believed that the heretofore neglected effect of incomplete ionization will have a significant impact on ultra-responsive phase shifters. A low V?L product of 0.3 V·cm associated with a low propagation loss of 20 dB/cm is expected to be observed. The phase shifter is based on overlapping implantation steps, where the doses and energies are carefully chosen to utilize counter-doping to produce an S-shaped junction. This junction has a particularly attractive V?L figure of merit, while simultaneously achieving attractively low capacitance and optical loss. This improvement will enable significantly smaller Mach-Zehnder modulators to be constructed that nonetheless would have low drive voltages, with substantial decreases in insertion loss. The described fabrication process is of minimal complexity; in particular, no high-resolution lithographic step is required.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 11, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Baehr-Jones, Yang Liu
  • Patent number: 10236399
    Abstract: Provided is a method of manufacturing a semiconductor device having a photodiode that has a shallow p-n junction and thus achieves high sensitivity to an ultraviolet ray, in which an oxide containing impurities at high concentration is deposited on the surface of the silicon substrate, and thereafter a diffusion region is formed to have a shallow junction by performing thermal diffusion of a rapid temperature change, with the use of a high-speed temperature rising and falling apparatus without using ion implantation into the silicon substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 19, 2019
    Assignee: ABLIC INC.
    Inventor: Tatsuya Aso
  • Patent number: 10211333
    Abstract: A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 19, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Madhur Bobde, Sik Lui
  • Patent number: 10141417
    Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 10096521
    Abstract: A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary E. Weybright, Robert C. Wong
  • Patent number: 10082686
    Abstract: A novel phase shifter design for carrier depletion based silicon modulators, based on an experimentally validated model, is described. It is believed that the heretofore neglected effect of incomplete ionization will have a significant impact on ultra-responsive phase shifters. A low V?L product of 0.3 V·cm associated with a low propagation loss of 20 dB/cm is expected to be observed. The phase shifter is based on overlapping implantation steps, where the doses and energies are carefully chosen to utilize counter-doping to produce an S-shaped junction. This junction has a particularly attractive V?L figure of merit, while simultaneously achieving attractively low capacitance and optical loss. This improvement will enable significantly smaller Mach-Zehnder modulators to be constructed that nonetheless would have low drive voltages, with substantial decreases in insertion loss. The described fabrication process is of minimal complexity; in particular, no high-resolution lithographic step is required.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: September 25, 2018
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Baehr-Jones, Yang Liu
  • Patent number: 10084036
    Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51).
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 25, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Shengrong Zhong, Dongfei Zhou, Xiaoshe Deng, Genyi Wang
  • Patent number: 10056462
    Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a surface, and an interlayer dielectric (ILD) defining a metal gate over the surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a capping layer, and a work function metal layer. A thickness of the capping layer sidewall distal to a corner of the capping layer, is substantially thinner than a thickness which is around center of the capping layer bottom. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate recess, forming a high-k dielectric layer, forming a first capping layer, forming a second capping layer on the first capping layer, removing or thinning down the first capping layer sidewall, and removing the second capping layer.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih Hsiung Lin, Chia-Der Chang, Fan-Yi Hsu, Pin-Cheng Hsu
  • Patent number: 9881994
    Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51).
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: January 30, 2018
    Assignee: CSMC Technologies Fabl Co., Ltd.
    Inventors: Shengrong Zhong, Dongfei Zhou, Xiaoshe Deng, Genyi Wang
  • Patent number: 9825122
    Abstract: A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a germanium oxide layer and a barrier layer over the work function stack, and annealing the germanium oxide layer to desorb oxygen therefrom to trigger oxidation of at least one conducting layer of the work function stack. The work function stack includes three layers, that is, a first layer being a TiN layer, a second layer being a titanium aluminum carbon (TiAlC) layer, and a third layer being a second TiN layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Patent number: 9564446
    Abstract: A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary E. Weybright, Robert C. Wong
  • Patent number: 8937349
    Abstract: A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: January 20, 2015
    Assignee: Sony Corporation
    Inventor: Koichi Amari
  • Patent number: 8883571
    Abstract: A method of manufacturing a transistor includes: forming an oxide semiconductor film and a gate electrode on a substrate, the oxide semiconductor film having a channel region, and the gate electrode facing the channel region; and forming an insulating film covering the gate electrode and the oxide semiconductor film. Infiltration of moisture from the insulating film into the oxide semiconductor film is suppressed by the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Narihiro Morosawa, Motohiro Toyota
  • Patent number: 8618615
    Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 31, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Se hyun Kim
  • Patent number: 8598623
    Abstract: A termination structure for a semiconductor device includes an array of termination cells formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In other embodiments, semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 3, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
  • Patent number: 8394714
    Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 12, 2013
    Assignee: Lexmark International, Inc.
    Inventor: Byron V. Bell
  • Patent number: 8134217
    Abstract: Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate, the first conductive region of a first conductivity type. A second conductive region is disposed on the first conductive region, the second conductive region of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 13, 2012
    Assignee: SunPower Corporation
    Inventors: Seung Bum Rim, Taeseok Kim, David D. Smith, Peter J. Cousins
  • Patent number: 8129778
    Abstract: Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: March 6, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Suku Kim, James J. Murphy, Gary Dolny
  • Patent number: 8119485
    Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Se hyun Kim
  • Patent number: 8093124
    Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: January 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Myung Shik Lee, Jin Gu Kim
  • Patent number: 7821100
    Abstract: A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting electrode and includes a fuse film configured to be torn by applying a predetermined current thereto. The protection target element electrode, the substrate connecting electrode and the fuse film are formed of an integral conductive film as long as the fuse film is not torn.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Higuchi, Keita Takahashi
  • Patent number: 7790568
    Abstract: A method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side of the channel region.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: September 7, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Tomohiro Okamura
  • Patent number: 7732311
    Abstract: In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Joo-Won Lee, Tae-Gyun Kim
  • Patent number: 7732861
    Abstract: A trench MOS type SiC semiconductor device includes a first conductivity semiconductor substrate, a first conductivity drift layer on the substrate, a second conductivity base layer on the drift layer, a first conductivity source layer on the base layer, a stripe shaped trench reaching from the surface of the source layer to the drift layer and having a gate electrode via a gate oxide film, a second conductivity layer on the bottom of the trench, and a second conductivity type region thereon on across-the-width side walls of at least one end of the trench, electrically coupling the second conductivity layer with the base layer. The device allows a low on-resistance without newly forming an electrode connected to the second conductivity layer even in the case of a device in which the second conductivity layer has to be grounded.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: June 8, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Takashi Tsuji
  • Patent number: 7667258
    Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kevin R. Shea, Chris W. Hill, Kevin J. Torek
  • Patent number: 7667289
    Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin
  • Publication number: 20100035422
    Abstract: Methods for forming doped regions in a semiconductor material that minimize or eliminate vapor diffusion of a dopant element and/or dopant from a deposited dopant and/or into a semiconductor material and methods for fabricating semiconductor devices that minimize or eliminate vapor diffusion of a dopant element and/or dopant from a deposited dopant and/or into a semiconductor material are provided. In one exemplary embodiment, a method for forming doped regions in a semiconductor material comprises depositing a conductivity-determining type dopant comprising a dopant element overlying a first portion of the semiconductor material. A diffusion barrier material is applied such that it overlies a second portion of the semiconductor material. The dopant element of the conductivity-determining type dopant is diffused into the first portion of the semiconductor material.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 11, 2010
    Applicant: HONEYWELL INTERNATIONAL, INC.
    Inventors: Roger Yu-Kwan Leung, De-Ling Zhou, Wenya Fan
  • Patent number: 7618867
    Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Tobias Mono, Frank Jakubowski, Hermann Sachse, Lars Voelkel, Klaus-Dieter Morhard, Dietmar Henke
  • Patent number: 7572708
    Abstract: A bipolar transistor device architecture and method of manufacture uses doped glass on the sidewall of the emitter window opening to reduce the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. The doped glass sidewall also improves dopant loss in the oxide in the case in which an in-situ doped poly emitter is used. By using a doped sidewall glass, the sensitivity of dopant absorption that can potentially occur in un-doped spacers is removed. The proposed technique also provides a simple method for achieving narrow emitter window openings while simultaneously improving doping uniformity compared to implanted poly techniques. The technique also allows a self-aligned base to be performed, thereby allowing tighter spacing between the extrinsic base and the intrinsic base.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: August 11, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Jeff A. Babcock, Steve Adler, Todd Thiebeault, Jamal Ramdani
  • Patent number: 7479434
    Abstract: A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: January 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Jo Kang, In-Sun Park, Dae-Joung Kim
  • Patent number: 7435628
    Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: October 14, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Yuri Mirgorodski, Vladislav Vashchenko, Peter Johnson
  • Patent number: 7303967
    Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: December 4, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hoon Sa
  • Patent number: 7205588
    Abstract: A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2 exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Chi-Hsi Wu, Shang Y. Hou
  • Patent number: 7189620
    Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N?-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N?-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N?-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N?-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N?-type silicon substrate (1).
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: March 13, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Takahashi, Shinji Aono
  • Patent number: 7087503
    Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: August 8, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Kamesh Gadepally
  • Patent number: 6849529
    Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: February 1, 2005
    Assignee: ProMOS Technologies Inc.
    Inventors: Yueh-Chuan Lee, Shih-Lung Chen