Through The Applied Layer (epo) Patents (Class 257/E21.15)
  • Patent number: 10497636
    Abstract: A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 3, 2019
    Assignee: AZ Power Inc.
    Inventors: Zheng Zuo, Bochao Huang, Ruigang Li, Da Teng
  • Patent number: 8846453
    Abstract: A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 30, 2014
    Assignee: Inpaq Technology Co., Ltd.
    Inventors: Chu-Chun Hsu, Wei-Luen Hsu, Hong-Sheng Ke, Yao-Ming Yang, Yu-Chia Chang
  • Patent number: 8748301
    Abstract: Provided are: a diffusing agent composition for ink-jet; a method for production of electrode and solar battery using the diffusing agent composition; and a solar battery produced by the method for production. The diffusing agent composition for ink-jet includes (a) a silicon compound, (b) an impurity-diffusing component and (c) a solvent, in which: the solvent (c) contains (c1) a solvent having a boiling point of no higher than 100° C. and (c2) a solvent having a boiling point of 180 to 230° C.; and the solvent (c1) is contained at a ratio of 70 to 90% by mass and the solvent (c2) is contained at a ratio of 1 to 20% by mass both relative to the total mass of the composition.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: June 10, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Toshiro Morita, Katsuya Tanitsu
  • Patent number: 8563409
    Abstract: A film-forming composition for use in a coating diffusion method, capable of diffusing a dopant at a higher concentration, and further capable of concomitantly forming a silica-based coating film is provided. A film-forming composition for constituting a diffusion film provided for diffusing a dopant element into a silicon wafer, the film-forming composition including: (A) a polymeric silicon compound; (B) an oxide of the dopant element, or a salt including the dopant element; and (C) porogene.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 22, 2013
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventor: Toshiro Morita
  • Patent number: 8530944
    Abstract: An object is to provide a semiconductor device which achieves miniaturization as well as suppressing a defect. Further, another object is to provide a semiconductor device which achieves miniaturization as well as keeping favorable characteristics. Is provided a semiconductor device including: a source wiring and a drain wiring each of which include a first conductive layer and a second conductive layer having a smaller thickness than the first conductive layer; an insulating layer which has an opening portion and is provided over the source wiring and the drain wiring; an oxide semiconductor layer which is in contact with part of the second conductive layer of the source wiring or the drain wiring in the opening portion; a gate insulating layer provided over the oxide semiconductor layer; and a gate electrode provided over the gate insulating layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20120187539
    Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 26, 2012
    Inventors: JOEL P. DE SOUZA, Marinus Hopstaken, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8114695
    Abstract: A method of producing a solid-state image pickup element includes forming a hole portion, forming a first-conductive type high-concentration impurity region in a bottom wall of the hole portion, and forming a first-conductive type high-concentration impurity-doped element isolation region in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region. The method also includes forming a second-conductive type photoelectric conversion region beneath the first-conductive type high-concentration impurity region and adapted to undergo a change in charge amount upon receiving light, and forming a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 14, 2012
    Assignee: Unisantis Electronics Singapore PTE Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20110195541
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: January 25, 2011
    Publication date: August 11, 2011
    Inventors: YOUICHI MACHII, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Takuya Aoyagi
  • Patent number: 7935618
    Abstract: Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Li Li
  • Patent number: 7598159
    Abstract: A method of fabricating a thin film transistor substrate includes forming a gate wiring on an insulating substrate and forming a gate insulating layer on the gate wiring; performing a first hydrogen plasma treatment with respect to the gate insulating layer; forming a first active layer with a first thickness at a first deposition rate on the gate insulating layer; performing a second hydrogen plasma treatment with respect to the first active layer; and forming a second active layer with a second thickness greater than the first thickness at a second deposition rate greater than the first deposition rate, on the first active layer.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa-yeul Oh, Byoung-june Kim, Sung-hoon Yang, Jae-ho Choi, Yong-mo Choi, Girotra Kunal
  • Publication number: 20090130811
    Abstract: A semiconductor device is manufactured by defining a groove in a semiconductor substrate, where the groove includes an upper portion and a lower portion, among other steps. A sacrificial layer is then formed to selectively fill the lower portion of the groove. Impurity ions are implanted into the semiconductor substrate while the lower portion of the groove is filled with the sacrificial layer. The sacrificial layer is then removed, and a gate is formed on the groove. In the method for manufacturing the semiconductor device, impurities can be doped at a uniform concentration in the channel area of the semiconductor device.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 21, 2009
    Inventor: Myung Hee KANG
  • Publication number: 20090108295
    Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.
    Type: Application
    Filed: April 24, 2008
    Publication date: April 30, 2009
    Inventors: Anthony Mowry, Markus Lenski, Guido Koerner, Ralf Otterbach
  • Patent number: 7303967
    Abstract: Disclosed is a method for fabricating a transistor of a semiconductor device, the method comprising the steps of: providing a semiconductor; forming a gate electrode; performing a low-density ion implantation process with respect to the substrate, thereby forming an LDD ion implantation layer; forming an insulation spacer on a sidewall of the gate electrode; forming a diffusion barrier; performing a high-density ion implantation process with respect to the substrate, thereby forming a source/drain; performing a first thermal treatment process with respect to a resultant structure, so as to activate impurities in the source/drain, and simultaneously causing a diffusion velocity of the impurities in the source/drain to be reduced by the diffusion barrier; and forming a salicide layer.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: December 4, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Hoon Sa
  • Patent number: 7148109
    Abstract: The present invention discloses a method for manufacturing a flash memory device which can minimize a hole current by impurity diffusion of floating gates, obtain a sufficient capacitance for a cell operation by increasing a breakdown voltage, and improve retention properties of a flash memory cell, by filing up an impurity on the interface between an oxide film and a polysilicon film, by forming the oxide film on the polysilicon film used as the floating gates, doping an impurity into the oxide film, and annealing the oxide film.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 12, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwang Chul Joo
  • Patent number: 7112539
    Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: September 26, 2006
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Jongho Lee, Nae-In Lee
  • Patent number: 7087503
    Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: August 8, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Kamesh Gadepally