Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

Abstract: This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate transistors. Implementation of a gate with sharp edges may improve the read and write speed and reduce the program and erase voltages in memory cells. It may also improve the gate control over the channel in tri-gate transistors and HEMTs. Methods to fabricate such devices are also disclosed.

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids.

Abstract: Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution having first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material having a regular pattern of micro-domains of the second polymer species within a polymer matrix having the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract: The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs—InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiOx-cladded Si quantum dots can also be used as high-k dielectric layer forming the gate insulator over the transport channel of a sub-22 nm FET.

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract: To provide a semiconductor device with nonvolatile memory, having improved performance. A memory cell has control and memory gate electrodes on a semiconductor substrate via an insulating film and another insulating film having first, second, and third films stacked one after another in order of mention, respectively. The memory and control gate electrodes are adjacent to each other via the stacked insulating film. The second insulating film has a charge accumulation function. The first and third insulating films each have a band gap greater than that of the second insulating film. An inner angle of the second insulating film between a portion extending between the semiconductor substrate and the memory gate electrode and a portion extending between the control gate electrode and the memory gate electrode is ?90°. An inner angle of the corner portion between the lower surface and the side surface of the memory gate electrode is <90°.

Abstract: A method for manufacturing a memory device may include obtaining a substrate structure that includes a substrate, an oxide material layer positioned on the substrate, a polysilicon material layer positioned on the oxide material layer, a first control gate and a second control gate positioned on the polysilicon material layer, and an offset oxide layer positioned between the first control gate and the second control gate. The method may further include the following steps: removing, using the offset oxide layer as a first mask, a portion of the polysilicon material layer for forming a polysilicon structure that includes a first step structure; forming a masking oxide layer on the offset oxide layer; removing, using the masking oxide layer as a second mask, a portion of the polysilicon structure for forming a floating gate polysilicon member that includes the first step structure and a second step structure.

Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.

Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.

Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

Abstract: A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers.

Abstract: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor. An air gap is provided between the sidewall film of the end memory cell and the sidewall film of the selective transistor.

Abstract: A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

Abstract: A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.

Abstract: A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.

Abstract: A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.

Abstract: A non-volatile memory includes a channel layer to extend from a substrate in a vertical direction; a plurality of interlayer dielectric layers and a plurality of gate electrodes to be alternately stacked along the channel layer; and a memory layer to be interposed between the channel layer and each of the gate electrodes, wherein the memory layer comprises a tunnel dielectric layer to contact the channel layer, a first charge trap layer to contact the tunnel dielectric layer and formed of an insulating material, a charge storage layer to contact the first charge trap layer and formed of a semiconducting material or a conductive material, a second charge trap layer to contact the charge storage layer and formed of an insulating material, and a charge blocking layer to contact the second charge trap layer.

Abstract: Methods for forming semiconductor memory structures including a gap between adjacent gate structures are provided. The methods may include forming an insulation layer between the adjacent gate structures. In some embodiments, the methods may include subsequently removing a portion of the insulation layer to leave the gap between the adjacent gate structures.

Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.

Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.

Abstract: A NAND flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates.

Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the floating gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the floating gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.

Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract: The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.

Abstract: A semiconductor memory device includes a memory cell block formed over a first memory cell region and a second memory cell region defined on a semiconductor substrate, and a voltage supply circuit configured to apply an operating voltage to gate lines of a plurality of memory cells included in the memory cell block, wherein a first air gap disposed between the gate lines in the first memory cell region has a smaller size than a second air gap disposed between the gate lines in the second memory cell region.

Abstract: A semiconductor memory device according to embodiment of the present invention includes a tunnel insulating layer formed over a semiconductor substrate, a floating gate formed over the tunnel insulating layer, a dielectric layer formed over the floating gate, and a control gate including a third silicon layer formed over the dielectric layer, a fourth silicon layer formed over the third silicon layer, and a conductive layer formed over the fourth silicon layer, wherein the fourth silicon layer has a greater width than the third silicon layer.

Abstract: The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.

Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.