Abstract: Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.

Abstract: In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

Abstract: Provided are a memory having a 3-dimensional structure and a method of fabricating the same, by which high integration density can be obtained. A contact region connected to a word line is formed to extend from a cell region in a first direction. A plurality of step difference layers constituting the contact region are formed to have step differences in a second direction different from the first direction. Also, provided is a method of fabricating a nonvolatile memory by which step differences are formed in a direction substantially perpendicular to a direction in which active regions are aligned. An insulating layer and etching layers are sequentially formed. By performing a selective etching process and pattern transfer, step differences are formed in a direction perpendicular to a direction in which multilayered active layers are disposed.

Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

Abstract: A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to create a reentrant profile in the second electrically conductive material layer and to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.

Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

Abstract: The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, forming sequentially a first high-k dielectric layer, an adjusting layer, a second high-k dielectric layer and a metal gate on the substrate, etching the first high-k dielectric layer, the adjusting layer, the second high-k dielectric layer and the metal gate to form a gate stack. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to arrange an adjusting layer between two layers of high-k dielectric layer, which effectively avoids reaction of the adjusting layer with the metal gate because of their direct contact, so as to maintain the performance of semiconductor devices.

Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.

Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.

Abstract: Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.

Abstract: In an embodiment, a semiconductor device includes a single-layer gate nonvolatile memory in which a floating gate is formed on a semiconductor substrate. The floating gate is formed above a diffusion layer serving as a control gate of the nonvolatile memory. The diffusion layer may be insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers may be formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film in an embodiment. The configuration described herein may realize a reliable semiconductor device in a low-cost process, may have a control gate which may withstand a high voltage applied when data is erased or written, and may prevent an operation error by minimizing variations in the threshold value, in some embodiments.

Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

Abstract: A method of manufacturing a nonvolatile memory device comprises providing a semiconductor substrate defining active regions and isolation regions with a gate insulating layer and a floating gate formed over each active region and isolation layer formed in the respective isolation regions, forming a dielectric layer on a surface of the isolation layers and the floating gates, forming a polysilicon layer over the dielectric layer through a polysilicon deposition process using a nitrogen source gas, a silicon source gas, and an impurity doping gas, and patterning the polysilicon layer to form a control gate.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract: A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching.

Abstract: Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

Abstract: A semiconductor device has a semiconductor substrate, a plurality of first conductive patterns, a second conductive pattern having a top surface of which stepwisely or gradually decreases in height in a direction from a side facing the first conductive pattern toward an opposite side, a first insulation film formed over the plurality of first conductive patterns and the second conductive pattern, and a third conductive pattern formed over the first insulation film.

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

Abstract: Methods for fabricating control gates in non-volatile storage are disclosed. When forming stacks for floating gate memory cells and transistor control gates, a sacrificial material may be formed at the top of the stacks. After insulation is formed between the stacks, the sacrificial material may be removed to reveal openings. In some embodiments, cutouts are then formed in regions in which control gates of transistors are to be formed. Metal is then formed in the openings, which may include the cutout regions. Therefore, floating gate memory cells having at least partially metal control gates and transistors having at least partially metal control gates may be formed in the same process. A barrier layer may be formed prior to depositing the metal in order to prevent silicidation of polysilicon in the control gates.

Abstract: A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Abstract: A method for fabricating a floating gate in a flash memory device includes providing a substrate, forming a first-type ion doped floating gate layer on the substrate, forming a first patterned photoresist layer on the first-type ion doped floating gate layer, dry etching the first patterned photoresist layer, wherein a dimension of the pattern of the first photoresist layer after the dry etching process is smaller than a dimension of the pattern before the dry etching process. The method further includes forming a dual-doped floating gate layer by implanting second-type ions into the first-type ion doped floating gate layer by using the first photoresist layer as a mask, wherein the first-type ions and the second-type ions have opposite charges. A flash memory device thus fabricated has a small CD and a dual-doped floating gate that provide high programming efficiency.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a third film so as to cover a second pattern, a second mask pattern, and a first film; etching back the third film to form a first sidewall line pattern along a sidewall of the second pattern and to form a first sidewall mask pattern along a sidewall of the second mask pattern; forming a third mask pattern comprising a resist film so as to cover the second mask pattern and the first sidewall mask pattern; and selectively removing the second pattern using the third mask pattern as a mask and thereafter removing the third mask pattern.

Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.

Abstract: A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.

Abstract: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.

Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

Abstract: A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells.

Abstract: A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate electrode, generated due to the floating gate electrode.

Abstract: A method of making a uniform nanoparticle array, including performing diblock copolymer thin film self assembly over a first dielectric on silicon, creating a porous polymer film, transferring a pattern into the first dielectric, selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

Abstract: A semiconductor memory device is provided including: a spacer shaped floating gate formed on a semiconductor substrate; a dielectric layer spacer formed at one side wall of the floating gate; a third oxide layer formed over the floating gate and the dielectric layer; and a control gate formed over the third oxide layer. According to an embodiment, the structure of the floating gate in a plate shape whose center is concave is improved to the spacer structure, making it possible to minimize the size of the semiconductor memory device and to improve density. Moreover, a LOCOS process can be excluded while forming the floating gate, making it possible to more efficiently fabricate the device.

Abstract: In accordance with an embodiment, a semiconductor device includes a functional film, first and second trenches, and first and second insulating films. The functional film comprises first and second areas. The first trench is provided in the first area of the functional film and has a first width. The second trench is provided in the second area of the functional film and has a second width larger than the first width. The first insulating film is formed from a polymeric material as a precursor to fill the first trench. The second insulating film has a diameter larger than the first width and is formed from particulates and the polymeric material as precursors. The particulates fill the second trench. The polymeric material fills spaces between the particulates in the second trench and also fills gaps between the particulates and the second trench.

Abstract: A method of forming a semiconductor device is disclosed. Nitrogen layers of an IPD stack are deposited using silane and a nitrogen plasma to yield a nitride layer plasma treated through its entire thickness. In addition to nitriding the bottom nitride layer of the stack, the middle nitride layer may also be nitrided. Depositing silicon from silane in a nitrogen plasma may be accomplished using high density plasma, ALD, or remote plasma processes. Elevated temperature may be used during deposition to reduce residual hydrogen in the deposited layer.

Abstract: A nonvolatile semiconductor memory includes a memory cell including, a semiconductor substrate, a first insulating layer on the semiconductor substrate, a floating gate on the first insulating layer, a second insulating layer on the floating gate, and a control gate electrode on the second insulating layer, wherein the floating gate is comprised a first conductive layer which is contact with the first insulating layer, a second conductive layer which is contact with the second insulating layer, and a semiconductor layer between the first and second conductive layers, and each of the first and second conductive layer is a metal layer or a silicide layer.

Abstract: Methods and apparatuses are disclosed for biasing the source-side and the drain-side of a nonvolatile memory to add electrons to the charge trapping structure.

Abstract: A method for forming a split gate flash cell device provides for forming floating gate transistors. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.

Abstract: To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.

Abstract: A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.

Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate, forming first spacers on sidewalls of the first trench, forming a second trench by etching the substrate under the first trench, forming second spacers on sidewalls of the second trench, forming a third trench, which has a wider width than a width between the second spacers, by etching the substrate under the second trench, forming a liner layer on the surface of the third trench, and exposing one of the sidewalls of the second trench by selectively removing the second spacers.

Abstract: A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.

Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device, having more than two types of threshold voltages, can be employed in a logic integrated circuit with an embedded SRAM. The semiconductor device can include at least two transistors. The two transistors can be the same conductivity type (e.g., n-type or p-type). In addition, the two transistors can have disparate voltage thresholds.