Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: Disclosed herein is a flash memory device comprising: a wafer; a gate oxide layer disposed upon the wafer; a floating gate disposed upon the gate oxide layer, the wafer, or a combination thereof; the floating gate comprising a flat floating gate portion and a generally rectangular floating gate portion disposed upon selected areas of the flat floating gate portion; a high K dielectric material disposed upon the floating gate; and a control gate disposed upon the high K dielectric material; wherein the high K dielectric material forms a zigzag pattern coupling the floating gate with the control gate.

Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

Abstract: A method of manufacturing a semiconductor memory device comprises providing a semiconductor substrate, forming gate lines over the semiconductor substrate, wherein each of the gate lines has a stack structure comprising an upper layer having a blocking layer formed on a polysilicon layer, forming a dielectric interlayer between the gate lines such that sides of the polysilicon layers of the gate lines are exposed, forming a metal layer on an entire surface of the dielectric interlayers, the blocking layers, and the polysilicon layers, causing the polysilicon layers in contact with the metal layer to react with the metal layer and undergo a phase change and become silicide layers, and removing the unreacted metal layer.

Abstract: Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

Abstract: A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.

Abstract: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.

Abstract: A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer.

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: A method for fabricating a flash memory device includes forming device isolation films in a semiconductor substrate, defining active regions between the device isolation films, and patterning floating gates on the semiconductor substrate to correspond to the active regions. Portions where the active regions and the floating gates are not overlap with one another are within reference offset ranges, respectively.

Abstract: An EEPROM device may have, at the region where the control gate is formed, a gate oxide layer having a relatively smaller thickness than the gate oxide layer of the tunneling region by removing the gate oxide layer, at a predetermined thickness, at the region where the control gate is formed. Thus, integration of an EEPROM device may be maximized as a result of minimizing the area of the control gate.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first polysilicon pattern formed on a semiconductor substrate, a second polysilicon pattern formed at a lateral side of the first polysilicon pattern such that the second polysilicon pattern extends to a height higher than the first polysilicon pattern, a third polysilicon pattern formed in a region restricted by a top surface of the first polysilicon pattern and a lateral side of the second polysilicon pattern, and a contact electrically connected with the second polysilicon pattern and the third polysilicon pattern.

Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.

Abstract: One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof.

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. The erase gate includes a notch, and the floating gate includes an edge that directly faces and is insulated from the notch.

Abstract: A BiCMOS substrate includes a bipolar area having a buried carrier layer, and a deep trench isolation (DTI) trench extending into the buried carrier layer to form a surface well implant above a buried well implant within the DTI trench, the buried well implant being the buried carrier layer portion within the DTI trench. A floating gate is disposed on the carrier well. Optionally, a high voltage control gate is formed of a stack of the buried well implant and the surface well implant within the DTI trench. Optionally, a poly layer formed of a bipolar process base poly layer is disposed on the floating gate. Optionally, a shallow well isolation region is formed on the substrate, a floating gate is disposed on the shallow well region, and an overlaying control gate, formed of a bipolar process base poly, is disposed above the floating gate.

Abstract: An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity regions formed apart from each other and a channel formation region provided between the impurity regions; and a first insulating film, a charge accumulating layer, a second insulating film, and a conductive film functioning as a gate electrode layer which are provided over the channel formation region. In the nonvolatile semiconductor storage device, a second barrier formed by the first insulating film against a charge of the charge accumulating layer is higher in energy than a first barrier formed by the first insulating film against a charge of the semiconductor film.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device, is achieved by forming a word gate on a gate insulating film which is formed on a wafer substrate; by forming charge accumulation films to cover a surface of the wafer substrate, side surfaces of the word gate and an upper surface of the word gate; by forming a conductive film to cover the charge accumulation film; and by forming control gates by etching the conductive film. The forming the control gates is achieved by setting an etching condition in which a bias power of 100 W to 1500 W is applied to a cathode electrode as a wafer stage on which the wafer substrate is arranged; and by performing anisotropic dry etching.

Abstract: A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and of realizing improved blocking function by forming the first oxide film including a silicon oxy-nitride (SiOxNy) layer using nitrous oxide (N2O) plasma, and by forming silicon-rich silicon nitride film, and a fabricating method thereof and a memory apparatus including the non-volatile memory device. Further, the non-volatile memory device can be fabricated on the glass substrate without using a high temperature process.

Abstract: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film and an edge portion of the gate electrode is rounded and oxidized.

Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: According to an aspect of the invention, there is provided a semiconductor device including a plurality of memory cells, comprising a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a semiconductor substrate and have an upper portion which is narrower in a channel width direction than a lower portion, an interelectrode insulating film formed on the floating gate electrodes, and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and partially buried between the floating gate electrodes opposing each other.

Abstract: A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient. Various process embodiments and completed structures are disclosed.

Abstract: A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

Abstract: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

Abstract: In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.

Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

Abstract: A semiconductor integrated circuit device includes first, second gate electrodes, first, second diffusion layers, contact electrodes electrically connected to the first diffusion layers, a first insulating film which has concave portions between the first and second gate electrodes and does not contain nitrogen as a main component, a second insulating film which is formed on the first insulating film and does not contain nitrogen as a main component, and a third insulating film formed on the first diffusion layers, first gate electrodes, second diffusion layers and second gate electrodes with the second insulating film disposed therebetween in a partial region. The second insulating film is formed to fill the concave portions and a portion between the first and second gate electrodes has a multi-layered structure containing at least the first and second insulating films.

Abstract: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.

Abstract: A method of forming a semiconductor device includes forming a trench on a semiconductor substrate to define an active region, forming a radical oxide layer on a sidewall and a bottom surface of the trench, and forming a nitride layer on the radical oxide layer. The conduction band offset of the radical oxide layer is greater than the conduction band offset of a thermal oxide layer having the same thickness as the radical oxide layer.

Abstract: A method of fabricating a semiconductor memory having word lines and bit lines disposed on a semiconductor substrate, with memory cells being formed at intersecting portions of the word lines and the bit lines. The method includes forming a first insulating film on the semiconductor substrate, forming a first polysilicon film on the first insulating film, patterning the first polysilicon film to form floating gates of the memory cells and an etching stop layer covering and surrounding contact portions of the word lines in a plan view, forming a second insulating film on the first polysilicon film, forming a conductive film on the second insulating film, patterning the conductive film to form control gates of the memory cells and strip-shaped regions as the word lines, accumulating an interlayer insulating film on the conductive film, and etching the interlayer insulating film, and opening contact holes for the contact portions.

Abstract: The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.

Abstract: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.

Abstract: Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

Abstract: A method of forming a gate line of a semiconductor device, wherein when an etch process for forming a gate line is performed, a loading effect is improved, thereby enhancing the operating speed of a semiconductor device. According to a method of forming a gate line of a semiconductor device in accordance with an aspect of the invention, a stack layer is formed over a semiconductor substrate that includes a first area and a second area. Hard mask patterns are formed over the stack layer so that the hard mask patterns are denser in the first area than in the second area. Next, a loading compensation layer is formed before the stack layer is etched, or the loading compensation layer is deposited after the stack layer is partially etched. Accordingly, a loading effect occurring when the stack layer is etched can be offset.

Abstract: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, forming a diffusion barrier for preventing metal diffusion over the insulation layer, forming a gate electrode layer over the diffusion barrier, forming a metal layer over the gate electrode layer, and performing a thermal treatment process on the substrate structure to form a metal silicide layer having a uniform thickness.

Abstract: This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the isolation trenches to form a solidified dielectric within the isolation trenches. The dielectric comprises carbon and silicon, and can be considered as having an elevationally outer portion and an elevationally inner portion within the isolation trenches. At least one of carbon removal from and/or oxidation of the outer portion of the solidified dielectric occurs. After such, the dielectric outer portion is etched selective to and effective to expose the dielectric inner portion. After the etching, dielectric material is deposited over the dielectric inner portion to within the isolation trenches.

Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.

Abstract: A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.

Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

Abstract: This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.

Abstract: Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.