With Gaseous Hydrogen Fluoride (hf) (epo) Patents (Class 257/E21.227)
  • Patent number: 10008587
    Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Toshihiko Saito, Takehisa Hatano, Hideomi Suzawa, Shinya Sasagawa, Junichi Koezuka, Yuichi Sato, Shinji Ohno
  • Patent number: 9018050
    Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 28, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Wen Huang
  • Patent number: 8906752
    Abstract: Ink compositions comprising polythiophenes and methicone that are formulated for inkjet printing the hole injecting layer (HIL) of an organic light emitting diode (OLED) are provided. Also provided are methods of inkjet printing the HILs using the ink compositions.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 9, 2014
    Assignee: Kateeva, Inc.
    Inventors: Inna Tregub, Rajsapan Jain, Michelle Chan
  • Patent number: 8895446
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Patent number: 8884441
    Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hung Hsueh, Wei-Te Wang, Shao-Yu Chen, Chun-Liang Fan, Kuan-Chi Tsai
  • Patent number: 8796131
    Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Edward E. Jones, Sharad N. Yedave, Ying Tang, Barry Lewis Chambers, Robert Kaim, Joseph D. Sweeney, Oleg Byl, Peng Zou
  • Patent number: 8785330
    Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Philippe Robert, Sophie Giroud
  • Patent number: 8785326
    Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Ming Zhang, Lifang Xu
  • Patent number: 8779479
    Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8765608
    Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8741702
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Miyuki Hosoba, Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8742544
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8723340
    Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 13, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler
  • Patent number: 8679922
    Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Takashi Usui
  • Patent number: 8664040
    Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng
  • Patent number: 8633116
    Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: January 21, 2014
    Assignee: Ulvac, Inc.
    Inventors: Manabu Yoshii, Kazuhiro Watanabe
  • Patent number: 8633105
    Abstract: A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 21, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 8603899
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: December 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8569821
    Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
  • Patent number: 8552501
    Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises semiconductor substrate, a first layer of a first semiconductor material over the semiconductor substrate and a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 8, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius Orlowski, Andreas Wild
  • Patent number: 8536699
    Abstract: In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Takashi Nakao, Ichiro Mizushima
  • Patent number: 8492264
    Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 23, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Patent number: 8486835
    Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 16, 2013
    Inventors: James E. Boyle, Reese Reynolds, Raanan Y. Zehavi, Tom L. Cadwell, Doris Mytton
  • Patent number: 8470095
    Abstract: A process for surface preparation of a substrate (2), which comprises introducing or running a substrate (2) into a reaction chamber (6, 106). A dielectric barrier (14, 114) is placed between electrodes (1, 10, 110). A high-frequency electrical voltage is generated, to generate filamentary plasma (12, 112). Molecules (8, 108) are introduced into the reaction chamber (6, 106). Upon contact with the plasma, they generate active species typical of reacting with the surface of the substrate. An adjustable inductor (L) placed in parallel with the inductor of the installation is employed to reduce the phase shift between the voltage and the current generated and to increase the time during which the current flows in the plasma (12, 112).
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 25, 2013
    Assignee: AGC Glass Europe
    Inventors: Eric Tixhon, Joseph Leclercq, Eric Michel
  • Patent number: 8410002
    Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 2, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8404052
    Abstract: A method for cleaning the surface of a silicon substrate, covered by a layer of silicon oxide includes: a) exposing the surface for 60 to 900 seconds to a radiofrequency plasma, generated from a fluorinated gas, to strip the silicon oxide layer and induce the adsorption of fluorinated elements on the substrate surface, the power density generated using the plasma being 10 mW/cm2 to 350 mW/cm2, the fluorinated gas pressure being 10 mTorrs to 200 mTorrs, and the substrate temperature being lower than or equal to 300° C.; and b) exposing the surface including the fluorinated elements for 5 to 120 seconds to a hydrogen radiofrequency plasma, to remove the fluorinated elements from the substrate surface, the power density generated using the plasma being 10 mW/cm2 to 350 mW/cm2, the hydrogen pressure being 10 mTorrs to 1 Torr, and the substrate temperature being lower than or equal to 300° C.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 26, 2013
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, Mario Moreno
  • Patent number: 8389399
    Abstract: A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: March 5, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Calvin Li, Christopher Petti
  • Patent number: 8389417
    Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8361873
    Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Ryota Imahayashi, Yoichi Iikubo, Kenichiro Makino, Sho Nagamatsu
  • Patent number: 8324119
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz
  • Patent number: 8304327
    Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
  • Patent number: 8269318
    Abstract: A method for forming an offset spacer of a MOS device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a dielectric stack on the substrate and the gate structure, wherein the dielectric stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer; and performing an etching process on the dielectric stack to form an offset spacer around the gate structure.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: September 18, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chun Rong
  • Patent number: 8242498
    Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: August 14, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Fumitake Nakanishi
  • Patent number: 8198194
    Abstract: Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: June 12, 2012
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd., International Business Machines Corporation
    Inventors: Jong Ho Yang, Hyung-rae Lee, Jin-Ping Han, Chung Woh Lai, Henry K. Utomo, Thomas W. Dyer
  • Patent number: 8183158
    Abstract: A method for using a semiconductor processing apparatus includes supplying an oxidizing gas and a reducing gas into a process container of the processing apparatus accommodating no product target substrate therein; causing the oxidizing gas and the reducing gas to react with each other within a first atmosphere that activates the oxidizing gas and the reducing gas inside the process container, thereby generating radicals; and removing a contaminant from an inner surface of the process container by use of the radicals.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: May 22, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masahiko Tomita, Kota Umezawa, Ryou Son, Toshiharu Nishimura
  • Patent number: 8158484
    Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate, and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: April 17, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius Orlowski, Andreas Wild
  • Patent number: 8153463
    Abstract: A method of manufacturing a thin film transistor substrate includes a first process in which a gate line pattern including a gate line and a gate electrode is formed with a first conductive material on a substrate using a first mask, a second process in which a first insulating layer is formed on the substrate and a data line pattern including a data line, a source electrode, and a drain electrode is formed with a second conductive material using a second mask, and a third process in which a second insulating layer is formed on the substrate and a pixel electrode connected to the drain electrode is formed on the second insulating layer with a third conductive material.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: April 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Kee Chin, Yunjong Yeo, Sanggab Kim, Junho Song, Kyehun Lee, Ho-Jun Lee
  • Patent number: 8138070
    Abstract: A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink containing a first set of nanoparticles and a first set of solvents, the first set of nanoparticles containing a first concentration of a first dopant. The method further includes depositing a second ink on a second surface of each of the first substrate and the second substrate, the second ink containing a second set of nanoparticles and a second set of solvents, the second set of nanoparticles containing a second concentration of a second dopant. The method also includes placing the first substrate and the second substrate in a back to back configuration; and heating the first substrate and the second substrate in a first drive-in ambient to a first temperature and for a first time period.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: March 20, 2012
    Assignee: Innovalight, Inc.
    Inventors: Maxim Kelman, Michael Burrows, Dmitry Poplavskyy, Giuseppe Scardera, Daniel Kray, Elena Rogojina
  • Patent number: 8084832
    Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: December 27, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Young-Je Yun
  • Patent number: 8071483
    Abstract: In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Takashi Nakao, Ichiro Mizushima
  • Patent number: 8048787
    Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
  • Patent number: 8035131
    Abstract: A method for forming a nitride semiconductor laminated structure includes forming a first layer that is an n-type or i-type first layer composed of a group III nitride semiconductor using an H2 carrier gas; forming a second layer by laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer using an H2 carrier gas; and forming a third layer that is an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer using an H2 carrier gas after forming the second layer. A method for manufacturing a nitride semiconductor device includes the method steps for forming the nitride semiconductor laminated structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Otake, Hiroaki Ohta, Shin Egami
  • Patent number: 7973345
    Abstract: A method of cleaning a patterning device, the patterning device having at least organic coating material (OLED material) deposited thereon, where the method includes the step of providing a cleaning plasma for removing the coating material from the patterning device by means of a plasma etching process. During the step of removing the coating material from the patterning device, the temperature of the patterning device does not exceed a critical temperature causing damage to the patterning device, while maintaining a plasma etching rate of at least 0.2 ?m/min. In order to generate a pulsed cleaning plasma, pulsed energy is provided. The method can be carried out in a direct plasma etching process or in a remote plasma etching process. Different etching processes may be combined or carried out subsequently.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: July 5, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Uwe Hoffmann, Jose Manuel Dieguez-Campo
  • Patent number: 7927972
    Abstract: Even if an oxygen ion implanted layer in a wafer for active layer is not a completely continuous SiO2 layer but a layer mixed partially with Si or SiOx, it is removed by here is provided a method for producing a bonded wafer in which it is possible to remove an oxygen ion implanted layer effectively as it is by repetitive treatment with an oxidizing solution and HF solution at a step of removing the oxygen ion implanted layer in a bonded wafer.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: April 19, 2011
    Assignee: Sumco Corporation
    Inventors: Akihiko Endo, Tatsumi Kusaba
  • Patent number: 7906439
    Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second regio
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: March 15, 2011
    Assignee: Commissarit a l'Energie Atomique
    Inventors: François Perruchot, Bernard Diem, Vincent Larrey, Laurent Clavelier, Emmanuel Defay
  • Patent number: 7863609
    Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: January 4, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Fumitake Nakanishi
  • Patent number: 7846845
    Abstract: A method and system for removing volatile residues from a substrate are provided. In one embodiment, the volatile residues removal process is performed en-routed in the system while performing a halogen treatment process on the substrate. The volatile residues removal process is performed in the system other than the halogen treatment processing chamber and a FOUP. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a vacuum tight platform, processing a substrate in a processing chamber of the platform with a chemistry comprising halogen, and treating the processed substrate in the platform to release volatile residues from the treated substrate.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: December 7, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth J. Bahng, Matthew Fenton Davis, Thorsten Lill, Steven H. Kim
  • Patent number: 7838400
    Abstract: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Peter Borden
  • Patent number: 7833887
    Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Jack Kavalieros
  • Patent number: 7829402
    Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 9, 2010
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Stephen Daley Arthur, Ramakrishna Rao, Peter Almern Losee, Zachary Matthew Stum