Abstract: A method of processing a workpiece includes a holding step, a height position detecting step, a modified layer forming step, and a dividing step. The height position detecting step is a step of, after the holding step, applying a measuring laser beam emitted from a height position detecting unit to the workpiece while moving a chuck table that holds the workpiece thereon and the height position detecting unit relatively to each other to detect a height position of the workpiece using a reflected beam from a reverse side of the workpiece. In the height position detecting step, the measuring laser beam is applied clear of areas of the workpiece where columnar conductive electrodes are embedded in streets.

Abstract: A topography simulation apparatus includes a processor and a memory connected to the processor. The memory stores instructions executable by the processor to set a function indicating a position relationship between a point in a calculation region and a material surface in the calculation region. The memory stores further instructions executable by the processor to determine whether or not a particle moving in the calculation region collides with the material surface, and update a value of the function, responsive to determining that the particle collides with the material surface.

Abstract: A micropump with a deformable membrane, including: a first chamber, one wall of which includes a first deformable membrane portion and an actuator of the first membrane portion; a second chamber including a second deformable membrane portion and a third chamber, including a third deformable membrane portion, the second chamber and the third chamber being connected together through a first channel, at least one of the second and third chambers being connected through a second channel to the first chamber; each of the second chamber and third chamber including a mechanism forming a detection gauge, but not including an activation mechanism.

Abstract: A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

Abstract: The present disclosure provides a capacitor structure, including a substrate having a conductive region; a trench in the conductive region and having a bottom portion and an inner sidewall portion; a spacer over the inner sidewall portion of the trench; a first conductive layer over the bottom portion and the spacer in the trench; a first dielectric layer over the first conductive layer and in the trench; a second conductive layer over the first dielectric layer and in the trench; and a second dielectric layer over the second conductive layer and in the trench, wherein the spacer comprises an angle in a range of from about 85 to about 89 degrees with respect to the bottom portion of the trench and comprises a flared opening opposite to the bottom portion of the trench. The present disclosure also provides a method for manufacturing the capacitor structure.

Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.

Abstract: A method for manufacturing a shallow trench isolation (STI) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench. A first dielectric layer is formed lining the trench. A second dielectric layer is formed filling the trench over the first dielectric layer. In some embodiments, before forming the second dielectric layer, ions are implanted into an implant region of the first dielectric layer that extends along and is limited to a lower region of the trench. In alternative embodiments, after forming the second dielectric layer, an ultraviolet curing process is performed to the second dielectric layer. With the second dielectric layer formed and, in some embodiments, the ultraviolet curing process completed, an annealing process is performed to the second dielectric layer. A semiconductor structure for a STI region is also provided.

Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract: A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain.

Abstract: An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.

Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.

Abstract: One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.

Abstract: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from the conductive layer, on the conductive layer; forming a photo-resist pattern of a fixed pattern on the mask layer; forming a mask pattern, which has an undercut shape to the photo-resist pattern, by etching the mask layer by use of the photo-resist pattern as an etching mask; removing the photo-resist pattern; and etching the conductive film by use of the mask pattern as an etching mask, to provide at least any one of the common electrode and the pixel electrode.

Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.

Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: Disclosed are a liquid crystal display device employing an amorphous zinc oxide-based semiconductor as an active layer, and a method for fabricating the same, whereby device stability can be secured by employing an etch stopper structure and device characteristics can be enhanced by minimizing exposure and deterioration of the active layer excluding content regions by virtue of the design of the etching stopper in a shape like “H”. Also, the liquid crystal display device and the fabrication method thereof can further form a semiconductor pattern and an insulating layer pattern on the intersection between the gate line and the data line, so as to compensate a stepped portion, thereby preventing an occurrence of short-circuit.

Abstract: A manufacturing method of thin film transistor substrate of a liquid crystal display panel includes following steps. A substrate is provided. Then, a transparent conducting layer and an opaque conducting layer are formed on the substrate. Thereafter, the transparent conducting layer and the opaque conducting layer are patterned by a gray-tone mask to form at least one storage capacitor electrode. Next, a first insulating layer is formed on the storage capacitor electrode. Then, at least one gate electrode is formed on the substrate. Subsequently, at least one gate insulating layer, a patterned semiconductor layer, a source electrode, a drain electrode, and a second insulating layer are formed sequentially on the gate electrode. Moreover, at least one pixel electrode is formed on the first insulating layer and the second insulating layer. A part of the pixel electrode overlaps a part of the storage capacitor electrode to form a storage capacitor.

Abstract: A method of fabricating a light-emitting element, in which less stress is applied to the light-emitting element, includes: forming element isolation patterns on a substrate; forming a buffer layer on an entire surface of the substrate to directly contact the surface of the substrate and the element isolation patterns and forming light-emitting structure layers on the buffer layer; forming element isolation trenches, which overlap at least part of the element isolation patterns, respectively, buffer layer patterns and light-emitting structures which are separated from each other by the element isolation trenches, respectively, by etching the buffer layer and the light-emitting structure layers; injecting a lift-off solution into the element isolation trenches to remove the element isolation patterns; and removing the substrate.

Abstract: A method for manufacturing a substrate for a liquid discharge head provided with a silicon substrate and a supply port, including: providing the silicon substrate having an insulating layer on a first surface and an etching mask layer having a plurality of apertures on a second surface which is a rear surface of the first surface, wherein the insulating layer is provided in a region ranging from a position opposing the apertures to a position opposing a portion between the adjacent apertures of the mask layer; and forming holes by etching a silicon part of the silicon substrate so that an etched region reaches a portion of the insulating layer opposing the apertures, wherein the silicon wall provided between the adjacent holes is etched so that the portion in the first surface side thereof can be thinner than the portion in the second surface side thereof.

Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

Abstract: A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.

Abstract: A method of forming a mask for use in fabricating an integrated circuit includes forming first non-removable portions of a photoresist material through a mask having a plurality of apertures, shifting the mask, forming second non-removable second portions of the photoresist material overlapping the first portions, and removing removable portions of the photoresist material arranged between the first and second portions. The formed photoresist mask may be used to form vias in an integrated circuit. The pattern of vias produced have the capability to exceed the current imaging resolution of a single exposure treatment.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

Abstract: A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.

Abstract: Provided are reinforced composite stamps, devices and methods of making the reinforced composite stamps disclosed herein. Reinforced composite stamps of certain aspects of the present invention have a composition and architecture optimized for use in printing systems for dry transfer printing of semiconductor structures, and impart excellent control over relative spatial placement accuracy of the semiconductor structures being transferred. In some embodiments, for example, reinforced composite stamps of the present invention allow for precise and repeatable vertical motion of the patterned surface of the printing apparatus with self-leveling of the stamp to the surface of a contacted substrate. Reinforced composite stamps of certain aspect of the present invention achieve a uniform distribution of contact forces between the printing apparatus patterned surface and the top surface of a substrate being contacted by the reinforced composite stamp of the printing apparatus.

Abstract: The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.

Abstract: A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

Abstract: A method for forming a micro-pattern in a semiconductor device includes forming a hard mask layer and a sacrificial layer over an etch target layer, forming a plurality of openings having a hole shape in the sacrificial layer, forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings, etching the sacrificial layer outside of the sidewalls of the openings using the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns, wherein the first area is smaller than the second area, and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns.

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract: The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected for its ability to be processed at a given desired temperature, has a layer of material applied to its surface. This layer is selected, among other reasons, for its ability to be molded. Typically, it is expected that the substrate will be able to withstand the higher temperatures of semiconductor post-processing whereas the applied layer will be moldable at low temperatures. This combination enables low cost embossing of a topography into this surface layer. The present invention comprises means to transfer this topography from the low temperature material into the higher temperature substrate.

Abstract: A CMOS structure includes a first device located using a first active region within a semiconductor substrate, where the first active region is planar and has a first crystallographic orientation. The CMOS structure also includes a second device that is located using a second active region within the semiconductor substrate, where the second active region is topographic and has a second crystallographic orientation absent the first crystallographic orientation. The first crystallographic orientation and the second crystallographic orientation allow for performance optimizations of the first device and the second device, typically with respect to charge carrier mobility. The topographic second active region may also have a single thickness. The CMOS structure may be fabricated using a crystallographically specific etchant for forming the topographic second active region.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.