Using Mask (epo) Patents (Class 257/E21.231)
E Subclasses
- Characterized by their behavior during process, e.g., soluble mask, redeposited mask (EPO) (Class 257/E21.234)
- Characterized by process involved to create mask, e.g., lift-off mask, sidewall, or to modify the mask, e.g., pre-treatment, post-treatment (EPO) (Class 257/E21.235)
- Process specially adapted to improve resolution of mask (EPO) (Class 257/E21.236)
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Patent number: 11887985Abstract: A method includes etching a substrate to form a semiconductor fin, forming a gate stack on a top surface and sidewalls of the semiconductor fin, and forming a first recess in the semiconductor fin on a side of the gate stack, wherein forming the first recess comprises, performing a first etching process to form a first portion of the first recess, depositing a first dielectric layer on sidewalls of the gate stack and the first portion of the first recess, performing a second etching process to form a second portion of the first recess using the first dielectric layer as a mask, wherein the second portion of the first recess extends under the gate stack, and performing a third etching process to remove the first dielectric layer.Type: GrantFiled: June 18, 2021Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yu-Rung Hsu
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Patent number: 10388857Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.Type: GrantFiled: June 16, 2016Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Armand A. Galan, Steve Holmes, Eric A. Joseph, Gen P. Lauer, Qinghuang Lin, Nathan P. Marchack
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Patent number: 9917203Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display apparatus are disclosed. The manufacturing method includes forming a gate electrode (2), a gate insulating layer (3), an active region (4), a source electrode (5) and a drain electrode (6) on a base substrate (1) with the active region being formed of ZnON material, and implanting the active region (4) with nitrogen ion while it being formed, so as to make the sub-threshold swing amplitude of the thin film transistor less than or equal to 0.5 mV/dec. The manufacturing method reduces the sub-threshold swing amplitude of the thin film transistor and improves the semiconductor characteristics of the thin film transistor.Type: GrantFiled: November 21, 2014Date of Patent: March 13, 2018Assignee: BOE Technology Group Co., Ltd.Inventors: Chunsheng Jiang, Lung Pao Hsin
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Patent number: 9012326Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.Type: GrantFiled: April 14, 2011Date of Patent: April 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gun Kim, Yoonjae Kim, Sungil Cho
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Patent number: 8999862Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.Type: GrantFiled: April 7, 2014Date of Patent: April 7, 2015Assignee: SK Hynix Inc.Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Hyung Lee, Hyun Kyung Shim, Chang Il Oh
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Patent number: 8999805Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.Type: GrantFiled: October 5, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
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Patent number: 8999848Abstract: A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.Type: GrantFiled: November 16, 2012Date of Patent: April 7, 2015Assignee: SK hynix Inc.Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Won Kyu Kim
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Patent number: 8981441Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.Type: GrantFiled: September 30, 2013Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
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Patent number: 8956976Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.Type: GrantFiled: February 4, 2014Date of Patent: February 17, 2015Assignee: Micron Technology, Inc.Inventors: William R. Brown, David Kewley, Adam Olson
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Patent number: 8956947Abstract: A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N?-type layer formed on an N+-type substrate. This trench is used to leave voids after the formation of a P?-type epitaxial film on the N?-type layer. Then, the voids formed in the N?-type layer can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.Type: GrantFiled: July 31, 2014Date of Patent: February 17, 2015Assignees: Sumco Corporation, Denso CorporationInventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Nobuhiro Tsuji, Toshiyuki Morishita
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Patent number: 8952452Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.Type: GrantFiled: December 3, 2012Date of Patent: February 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Seong Kang, Yoon-Hae Kim, Jong-Shik Yoon
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Patent number: 8907375Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.Type: GrantFiled: March 29, 2013Date of Patent: December 9, 2014Assignee: Sony CorporationInventor: Masashi Yanagita
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Patent number: 8884377Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.Type: GrantFiled: February 18, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
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Patent number: 8828868Abstract: A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask.Type: GrantFiled: December 7, 2011Date of Patent: September 9, 2014Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventor: Zhongshan Hong
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Patent number: 8791020Abstract: A pattern-forming method includes forming a silicon-containing film on a substrate, the silicon-containing film having a mass ratio of silicon atoms to carbon atoms of 2 to 12. A shape transfer target layer is formed on the silicon-containing film. A fine pattern is transferred to the shape transfer target layer using a stamper that has a fine pattern to form a resist pattern. The silicon-containing film and the substrate are dry-etched using the resist pattern as a mask to form a pattern on the substrate in nanoimprint lithography. According to another aspect of the invention, a silicon-containing film includes silicon atoms and carbon atoms. A mass ratio of silicon atoms to carbon atoms is 2 to 12. The silicon-containing film is used for a pattern-forming method employed in nanoimprint lithography.Type: GrantFiled: July 28, 2011Date of Patent: July 29, 2014Assignee: JSR CorporationInventors: Takashi Mori, Masato Tanaka, Yukio Nishimura, Yoshikazu Yamaguchi
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Patent number: 8778805Abstract: In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.Type: GrantFiled: January 30, 2012Date of Patent: July 15, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Seiya Fujii
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Patent number: 8772166Abstract: Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.Type: GrantFiled: June 19, 2012Date of Patent: July 8, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej Sandhu, Mark Kiehlbauch, Steve Kramer, John Smythe
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Patent number: 8759233Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.Type: GrantFiled: June 21, 2012Date of Patent: June 24, 2014Assignee: Hynix Semiconductor Inc.Inventor: Sang Hoon Cho
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Patent number: 8759225Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.Type: GrantFiled: September 4, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung Chien Wang, Yeur-Luen Tu, Cheng-Ta Wu, Jiech-Fun Lu, Chun-Wei Chang, Wang-Pen Mo, Jhy-Jyi Sze, Chia-Shiung Tsai
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Patent number: 8735985Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.Type: GrantFiled: December 13, 2012Date of Patent: May 27, 2014Assignee: The Invention Science Fund I, LLCInventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
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Patent number: 8729658Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.Type: GrantFiled: March 7, 2013Date of Patent: May 20, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Kwang-Youl Chun, Sang-Bin Ahn
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Patent number: 8729707Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.Type: GrantFiled: October 4, 2012Date of Patent: May 20, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Wensheng Wang
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Patent number: 8703616Abstract: Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sidewalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled.Type: GrantFiled: May 19, 2008Date of Patent: April 22, 2014Assignee: Round Rock Research, LLCInventor: David H. Wells
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Publication number: 20140091434Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: MICRON TECHNOLOGY, INC.Inventor: John D. Hopkins
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Patent number: 8679922Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.Type: GrantFiled: January 27, 2012Date of Patent: March 25, 2014Assignee: Canon Kabushiki KaishaInventors: Takaharu Kondo, Takashi Usui
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Patent number: 8673780Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.Type: GrantFiled: August 2, 2011Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventors: William R. Brown, David A. Kewley, Adam Olson
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Publication number: 20140065831Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Inventors: Carolyn R. Ellinger, David H. Levy, Shelby F. Nelson
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Patent number: 8647896Abstract: Provided is a process for producing a substrate for a liquid ejection head, including forming a liquid supply port in a silicon substrate, the process including the steps of (a) forming an etch stop layer at a portion of a front surface of the silicon substrate at which portion the liquid supply port is to be formed; (b) performing dry etching using a Bosch process from a rear surface side of the silicon substrate up to the etch stop layer with use of an etching mask formed on a rear surface of the silicon substrate to thereby form the liquid supply port; and (c) simultaneously removing the etch stop layer and a deposition film formed inside the liquid supply port.Type: GrantFiled: March 5, 2012Date of Patent: February 11, 2014Assignee: Canon Kabushiki KaishaInventor: Toshiyasu Sakai
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Publication number: 20140038412Abstract: Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Xiang Hu, Mingmei Wang, Liu Huang
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Publication number: 20140027917Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
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Publication number: 20140024213Abstract: Processes for forming an integrated circuit are provided. In an embodiment, a process for forming an integrated circuit includes forming a low-k dielectric layer overlying a base substrate. An etch mask is patterned over the low-k dielectric layer. A recess is etched into the low-k dielectric layer through the etch mask to expose a recess surface within the recess. The low-k dielectric layer and the base substrate are annealed after etching. Annealing is conducted in an annealing environment, such as in an annealing furnace that provides the annealing environment. The recess surface is exposed to the annealing environment. An electrically-conductive material is deposited in the recess after annealing to form an embedded electrical interconnect.Type: ApplicationFiled: July 18, 2012Publication date: January 23, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Bernd Hintze, Frank Koschinsky, Uwe Stoeckgen
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Publication number: 20140024147Abstract: A MEMS device fabrication method includes providing a substrate and a chamber wall material layer on a first surface of the substrate, the chamber wall material layer including a chamber cavity having a sacrificial material located therein. A mask material is deposited on the chamber wall material layer and the sacrificial material and patterned to form a mask pattern including a plurality of discrete portions. The mask material and some of the sacrificial material are removed to transfer the mask pattern including the plurality of discrete portions to the sacrificial material. A membrane material layer is deposited on the chamber wall material layer and the sacrificial material that includes the transferred mask pattern including the plurality of discrete portions. Some of the substrate and the sacrificial material are removed to release the membrane material layer using at least one process initiated from a second surface of the substrate.Type: ApplicationFiled: July 19, 2012Publication date: January 23, 2014Inventors: Yonglin Xie, Weibin Zhang
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Patent number: 8633116Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.Type: GrantFiled: January 25, 2011Date of Patent: January 21, 2014Assignee: Ulvac, Inc.Inventors: Manabu Yoshii, Kazuhiro Watanabe
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Patent number: 8598037Abstract: A method of etching a silicon layer through a patterned mask is provided. The method uses an etch chamber in which the silicon layer is placed. The method includes (a) providing the silicon layer having the patterned mask formed thereon, (b) providing an etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas into the etch chamber in which the silicon layer has been placed, (c) generating a plasma from the etch gas, (d) etching features into the silicon layer through the patterned mask using the plasma, and (e) stopping the etch gas. The oxygen and hydrogen containing gas contains water vapor.Type: GrantFiled: December 28, 2011Date of Patent: December 3, 2013Assignee: Lam Research CorporationInventors: Jaroslaw W. Winniczek, Robert P. Chebi
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Patent number: 8574926Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.Type: GrantFiled: September 18, 2011Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
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Patent number: 8574942Abstract: A method of preparing a silicon nanowire and a method of fabricating a lithium secondary battery including the silicon nanowire are provided. The method of preparing a silicon nanowire may include forming a catalyst layer including metal particles separated from one another on a silicon layer, selectively etching the silicon layer contacting the metal particles, and removing the metal particles.Type: GrantFiled: October 12, 2012Date of Patent: November 5, 2013Assignee: Unist Academy-Industry Research CorporationInventors: Soojin Park, Byoungman Bang, Jung-Pil Lee, Hyun-Kon Song, Jaephil Cho
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Publication number: 20130285263Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.Type: ApplicationFiled: September 30, 2012Publication date: October 31, 2013Applicant: APPLE INC.Inventors: Shawn X. ARNOLD, Terry L. GILTON, Matthew LAST
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Patent number: 8569821Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.Type: GrantFiled: September 23, 2011Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
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Publication number: 20130277823Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Inventors: Kiyonori Ogisu, Yosuke Takahata
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Patent number: 8563373Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.Type: GrantFiled: August 26, 2009Date of Patent: October 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
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Patent number: 8557661Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.Type: GrantFiled: December 8, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Geun Yu, Gyung-Jin Min, Seong-Soo Lee, Suk-Ho Joo, Yoo-Chul Kong, Dae-Hyun Jang
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Patent number: 8551836Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.Type: GrantFiled: May 16, 2011Date of Patent: October 8, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Wensheng Wang
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Publication number: 20130260568Abstract: A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas.Type: ApplicationFiled: August 8, 2012Publication date: October 3, 2013Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Jae Seung HWANG, Jae-Won LEE, Jun SEO
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Patent number: 8546258Abstract: Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.Type: GrantFiled: May 31, 2012Date of Patent: October 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-cheol Kim, Dae-youp Lee
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Publication number: 20130244430Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Chih-Han Lin
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Patent number: 8530932Abstract: A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess.Type: GrantFiled: March 21, 2012Date of Patent: September 10, 2013Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Amlan Majumdar
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Patent number: 8518835Abstract: Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes subunits A and B, and will be self-assembled to form core structures spaced center-to-center by a distance of L0. The core structures are contained within a repeating pattern of polygonal unit cells. Distances from the core structures to various locations of the unit cells are calculated to determine desired distributions of subunit lengths.Type: GrantFiled: August 20, 2012Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventor: Scott E. Sills
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Patent number: 8513717Abstract: A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode.Type: GrantFiled: December 16, 2011Date of Patent: August 20, 2013Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Publication number: 20130193565Abstract: Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chiang Tu, Chun-Lang Chen, Boming Hsu, Tran-Hui Shen
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Publication number: 20130196508Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.Type: ApplicationFiled: January 26, 2012Publication date: August 1, 2013Applicant: GLOBALFOUNDRIES INC.Inventor: Nicholas V. LiCausi