By Ion Implantation (epo) Patents (Class 257/E21.248)
  • Patent number: 10336023
    Abstract: The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least: a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411?, 411?) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step; c) a step of removing (461, 462) the modified zones (411
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 2, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Stefan Landis, Lamia Nouri
  • Patent number: 10109952
    Abstract: A connector includes a first housing, a second housing, a mate assist slider, and a cam gear. The first-housing has a first outer surface. The second housing is configured to mate with the first housing, and the second housing includes a pin extending from a second outer surface. The connector also includes a mate assist slider moveable from an unmated position to a mated position. The connector also includes a cam gear mounted to the first outer surface. The cam gear moves in response to a movement of the mate-assist-slider from the unmated position to the mated position. The cam gear has a cam slot with an inertial detent. A vibratory feedback is provided to an assembler indicative of a properly positioned connector housing when the pin is moved past the inertial detent.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 23, 2018
    Assignee: Delphi Technologies, LLC
    Inventors: Jeffrey Scott Campbell, Wesley W. Weber, Jr.
  • Patent number: 9953989
    Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited and National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9768064
    Abstract: Formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a low topography region and a high low topography region. The method also includes forming a first dielectric layer over the substrate. The method further includes forming a second dielectric layer over the stop layer. In addition, the method includes forming an opening in the first dielectric layer, the stop layer and the second dielectric layer. The method also includes forming a conductive material layer over the second dielectric layer. The conductive material layer fills the opening. The method further includes performing a polishing process over the conductive material layer until a top surface of the stop layer is exposed.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Wei Hsu, Chi-Jen Liu, Cheng-Chun Chang, Yi-Sheng Lin, Liang-Guang Chen
  • Patent number: 9231098
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Chun Wang, Yi-Chun Lo, Chia-Der Chang, Guo-Chiang Chi, Chia-Ping Lo, Fu-Kai Yang, Hung-Chang Hsu, Mei-Yun Wang
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Patent number: 8999863
    Abstract: A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 7, 2015
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jae Gon Lee, Jingze Tian, Shyue Seng Tan, Luona Goh, Wei Lu, Elgin Quek
  • Patent number: 8907375
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Sony Corporation
    Inventor: Masashi Yanagita
  • Patent number: 8906708
    Abstract: A method for checking an ion implantation condition when ions are implanted over an entirety of one surface of a semiconductor wafer having an insulator film on the one surface, the method including checking whether the ions are implanted over the entirety of the one surface of the semiconductor wafer by directly or indirectly observing light emitted when the one surface of the semiconductor wafer is irradiated with an ion beam of the implanted ions throughout the ion implantation.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: December 9, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Isao Yokokawa
  • Patent number: 8796131
    Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Edward E. Jones, Sharad N. Yedave, Ying Tang, Barry Lewis Chambers, Robert Kaim, Joseph D. Sweeney, Oleg Byl, Peng Zou
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Patent number: 8664691
    Abstract: A silicon photomultiplier maintains the photon detection efficiency high while increasing a dynamic range, by reducing the degradation of an effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 4, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Joon Sung Lee
  • Patent number: 8587041
    Abstract: According to one embodiment, a solid-state imaging device includes an imaging region including unit pixels which are two-dimensionally arranged on a semiconductor layer and each of which includes a photoelectric conversion unit and a signal scanning circuit unit. The unit pixel includes a transfer gate provided on the semiconductor layer, a photogate provided on the semiconductor layer, a first semiconductor layer of a first conductivity type, which is provided in the semiconductor layer below the photogate, and a second semiconductor layer of the first conductivity type, which is adjacent to the first semiconductor layer and provided in the semiconductor layer between the transfer gate and the photogate.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ai Mochizuki, Takeshi Yoshida
  • Patent number: 8569821
    Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
  • Patent number: 8536031
    Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
  • Patent number: 8513717
    Abstract: A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 20, 2013
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8497208
    Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
  • Patent number: 8481393
    Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaki Koyama, Fumito Isaka, Akihisa Shimomura, Junpei Momo
  • Patent number: 8466064
    Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: June 18, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
  • Patent number: 8426287
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 23, 2013
    Assignee: Sony Corporation
    Inventor: Masashi Yanagita
  • Patent number: 8415223
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: April 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
  • Patent number: 8372760
    Abstract: A system and method for forming a mechanically strengthened low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. An upper surface of the low-k dielectric film is then treated in order to increase the film's mechanical strength, or reduce its dielectric constant.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: February 12, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Kenneth Duerksen, David A. Vidusek
  • Patent number: 8293659
    Abstract: A method for fabricating a dielectric layer with improved insulating properties is provided, including: providing a dielectric layer having a first resistivity; performing a hydrogen plasma doping process to the dielectric layer; and annealing the dielectric layer, wherein the dielectric layer has a second resistivity greater than that of the first resistivity after annealing thereof.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 23, 2012
    Assignee: Nanya Technology Corporation
    Inventor: Shu Qin
  • Patent number: 8293660
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist pattern on an insulating film formed on a semiconductor substrate by applying a photoresist on the insulating film; processing the insulating film by removing an unnecessary portion of the insulating film by wet etching; and implanting ions into the insulating film before and/or after forming the photoresist pattern. In implanting the ions, the depth of a damaged region formed in the insulating film by implanting the ions is changed in accordance with the presence or absence of the photoresist pattern.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: October 23, 2012
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Kei Tamura, Koji Miyoshi
  • Patent number: 8193592
    Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: June 5, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
  • Patent number: 8138064
    Abstract: A method for producing a silicon film-transferred insulator wafer is disclosed. The method includes a surface activation step of performing a surface activation treatment on at least one of a surface of an insulator wafer and a hydrogen ion-implanted surface of a single crystal silicon wafer into which a hydrogen ion has been implanted to form a hydrogen ion-implanted layer; a bonding step that bonds the hydrogen ion-implanted surface to the surface of the insulator wafer to obtain bonded wafers; a first heating step that heats the bonded wafers; a grinding and/or etching step of grinding and/or etching a surface of a single crystal silicon wafer side of the bonded wafers; a second heating step that heats the bonded wafers; and a detachment step to detach the hydrogen ion-implanted layer by applying a mechanical impact to the hydrogen ion-implanted layer of the bonded wafers thus heated at the second temperature.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: March 20, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
  • Patent number: 8101492
    Abstract: One or more embodiments relate to a method of forming a semiconductor device, including: providing a substrate; forming a gate stack over the substrate, the gate stack including a control gate over a charge storage layer; forming a conductive layer over the gate stack; etching the conductive layer to remove a portion of the conductive layer; and forming a select gate, the forming the select gate comprising etching a remaining portion of the conductive layer.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 24, 2012
    Assignee: Infineon Technologies AG
    Inventors: John Power, Danny Pak-Chum Shum
  • Patent number: 8093640
    Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 10, 2012
    Assignee: Atmel Corporation
    Inventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
  • Patent number: 8084312
    Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: December 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, P R Chidambaram, Rajesh Khamankar, Haowen Bu, Douglas T. Grider
  • Patent number: 8048787
    Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
  • Patent number: 8039374
    Abstract: Techniques for low temperature ion implantation are provided to improve throughput. Specifically, the pressure of the backside gas may temporarily, continually or continuously increase before the starting of the implant process, such that the wafer may be quickly cooled down from room temperature to be essentially equal to the prescribed implant temperature. Further, after the vacuum venting process, the wafer may wait an extra time in the load lock chamber before the wafer is moved out the ion implanter, in order to allow the wafer temperature to reach a higher temperature quickly for minimizing water condensation on the wafer surface. Furthermore, to accurately monitor the wafer temperature during a period of changing wafer temperature, a non-contact type temperature measuring device may be used to monitor wafer temperature in a real time manner with minimized condensation.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: October 18, 2011
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventors: John D. Pollock, Zhimin Wan, Erik Collart
  • Patent number: 8021936
    Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Takashi Noguchi, Wenxu Xianyu, Hans S. Cho, Huaxiang Yin
  • Patent number: 8022450
    Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a first pixel having a first photodiode and a first readout circuit and a second pixel having a second photodiode and a second readout circuit. The second pixel is aligned at one side of the first pixel, and a light receiving area of the first photodiode is different from a light receiving area of the second photodiode.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: September 20, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Gun Hyuk Lim
  • Publication number: 20110210427
    Abstract: In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.
    Type: Application
    Filed: November 2, 2010
    Publication date: September 1, 2011
    Inventors: Jan Hoentschel, Sven Beyer, Uwe Griebenow, Thilo Scheiper
  • Patent number: 8003531
    Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 23, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chung-Kyung Jung
  • Patent number: 7977185
    Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: July 12, 2011
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
  • Patent number: 7964900
    Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: June 21, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, Hsu Chen Cheng
  • Patent number: 7947607
    Abstract: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: May 24, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Chao-I Wu
  • Patent number: 7939388
    Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Hisao Nagai, Yuichiro Sasaki, Katsumi Okashita, Hiroyuki Ito, Bunji Mizuno
  • Patent number: 7923360
    Abstract: A method of forming dielectric films including a metal silicate on a silicon substrate comprises a first step of oxidizing a surface layer portion of the silicon substrate and forming a silicon dioxide film; a second step of irradiating ion on the surface of the silicon dioxide film and making the surface layer portion of the silicon dioxide film into a reaction-accelerating layer with Si—O cohesion cut; a third step of laminating a metal film on the reaction-accelerating layer in a non-oxidizing atmosphere; and a fourth step of oxidizing the metal film and forming a metal silicate film that diffuses a metal from the metal film to the silicon dioxide film.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 12, 2011
    Assignees: Canon Kabushiki Kaisha, Canon Anelva Corporation
    Inventors: Hideo Kitagawa, Naomu Kitano
  • Patent number: 7915128
    Abstract: A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using photolithography techniques. The photoresist material is removed prior to etching the underlying conductive layer and dielectric layer. The hard mask is also used as an implant mask. Another mask may be deposited and formed over the conductive layer to form other devices in other regions of the substrate. The other mask is preferably removed from over the hard mask prior to etching the conductive layer and the dielectric layer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Wen Chen, Fu-Hsin Chen, Ming-Ren Tsai, William Wei-Yuan Tien
  • Patent number: 7906834
    Abstract: A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: March 15, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Toshiyuki Mine, Mitsuharu Tai, Akio Shima
  • Patent number: 7892934
    Abstract: On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate as bonding surfaces are brought into close contact with each other, and bonding is performed by heating the substrates in this state at a temperature of 350° C. or below. After this bonding process, an Si—Si bond in the ion implantation layer is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (L) in the vicinity of the surface of the single crystal Si substrate.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: February 22, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Yuuji Tobisaka, Shoji Akiyama
  • Publication number: 20110024819
    Abstract: Improved high quality gate dielectrics and methods of preparing such dielectrics are provided. Preferred dielectrics comprise a rare earth doped dielectric such as silicon dioxide or silicon oxynitride. In particular, cerium doped silicon dioxide shows an unexpectedly high charge-to-breakdown QBD, believed to be due to conversion of excess hot electron energy as photons, which reduces deleterious hot electron effects such as creation of traps or other damage. Rare earth doped dielectrics therefore have particular application as gate dielectrics or gate insulators for semiconductor devices such as floating gate MOSFETs, as used in as flash memories, which rely on electron injection and charge transfer and storage.
    Type: Application
    Filed: June 14, 2010
    Publication date: February 3, 2011
    Inventors: Carla Miner, Thomas MacElwee, Marwan Albarghouti
  • Patent number: 7879666
    Abstract: A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 1, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Chendong Zhu, Xiangdong Chen, Melanie Sherony
  • Patent number: 7867836
    Abstract: A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: January 11, 2011
    Assignee: Honda Motor Co., Ltd.
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito
  • Patent number: 7851318
    Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaki Koyama, Fumito Isaka, Akihisa Shimomura, Junpei Momo
  • Patent number: 7829401
    Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: November 9, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
  • Patent number: 7829402
    Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 9, 2010
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Stephen Daley Arthur, Ramakrishna Rao, Peter Almern Losee, Zachary Matthew Stum
  • Patent number: 7824994
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen