Abstract: Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor gas into the process chamber during the ALD process to produce the target characteristic in the layer of material, and performing the ALD process that comprises a plurality of steps wherein the precursor gas is introduced into the chamber for the determined precursor pulse time to thereby form the layer of material.

Abstract: One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least

Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.

Abstract: A method for forming an integrated circuit device including an interconnect structure, e.g., copper dual damascene. The method includes providing a substrate and forming an interlayer dielectric layer overlying the substrate. The method also includes patterning the interlayer dielectric layer to form a contact structure and forming a barrier metal layer overlying the contact structure. The method includes forming a seed layer comprising copper bearing species overlying the barrier metal layer and applying an oxygen bearing species to treat the seed layer to cause an oxide layer of predetermined thickness to form on the seed layer. The method protects the seed layer from contamination using the oxide layer while the substrate is transferred from the step of applying the seed layer and contacts a copper bearing material in liquid form overlying the oxide layer to dissolve the oxide layer while forming a thickness of copper bearing material using a plating process to begin filling the contact structure.

Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.

Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.

Abstract: A method for forming a metal silicate as a high k dielectric in an electronic device, comprising the steps of: providing diethylsilane to a reaction zone; concurrently providing a source of oxygen to the reaction zone; concurrently providing a metal precursor to the reaction zone; reacting the diethylsilane, source of oxygen and metal precursor by chemical vapor deposition to form a metal silicate on a substrate comprising the electronic device. The metal is preferably hafnium, zirconium or mixtures thereof. The dielectric constant of the metal silicate film can be tuned based upon the relative atomic concentration of metal, silicon, and oxygen in the film.

Abstract: The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR1)(NR2R3)3, wherein each R1, R2, and R3 is independently hydrogen or an organic group, with the proviso that at least one of R1, R2, and R3 is a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Abstract: A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line.

Abstract: Methods and compositions for depositing a metal containing thin film on a substrate comprises introducing a vapor phase metal-organic precursor into a reaction chamber containing one or more substrates. The precursor has at least one ?-diketiminato ligand, and has the general formula: M(R1C(NR4)CR2C(NR5)R3)2Ln wherein M is a metal selected from nickel, cobalt, ruthenium, iridium, palladium, platinum, silver and gold. Each of R1-5 is an organic ligand independently selected from H; and a C1-C4 linear or branched, alky group, alkylsilyl group, alkylamide group, alkoxide group, or alkylsilylamide group. Each L is independently selected from: a hydrocarbon; an oxygen-containing hydrocarbon; an amine; a polyamine; a bipyridine; an oxygen containing heterocycle; a nitrogen containing heterocycle; and combinations thereof; and n is an integer ranging from 0 to 4, inclusive. A metal containing film is deposited onto the substrate, while the substrate is maintained at a temperature between about 100° C.

Abstract: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.

Abstract: Disclosed is a group III nitride compound semiconductor device having a substrate, buffer layers on the substrate, and a group III nitride compound semiconductor layer on the top layer of the buffer layers. The buffer layers comprises a first buffer layer formed on the substrate and a second buffer layer formed on the first buffer layer. The first buffer layer is made of transition metal nitride, and the second buffer layer is made of nitride of gallium and a transition metal.

Abstract: A substrate 10 for a semiconductor device includes: a base plate 1, a plurality of external terminal portions 12p, 12q, respectively arranged in a plane on the base plate 1 and having external terminal faces 12pb, 12qb respectively facing the base plate 1; a plurality of internal terminal portions 11, respectively arranged in the plane on the base plate 1 and having internal terminal faces 11a respectively facing an opposite side to the base plate 1. The internal terminal portions 11 are connected with the external terminal portions 12p, 12q, via wiring portions 17, respectively. A part of the external terminal portions 12p are located on the base plate 1 in a predetermined arrangement area A in which a semiconductor element 50 is arranged.

Abstract: In an embodiment, a method of creating an alignment mark on a substrate includes forming a plurality of lines segmented into electrically conducting line segments and space segments, thereby forming spaces between the lines to form a macroscopic structure in a first layer of the substrate, creating a plurality of electrically conducting trenches in a second layer of the substrate, and arranging the plurality of trenches to be in electrical contact with the line segments and overlapping the space segments at least partially.

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the first semiconductor layer, forming a support in the first groove, etching the second semiconductor layer to form a second groove that exposes the first semiconductor layer, forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove, forming a semiconductor film in the cavity, and thermally oxidizing the semiconductor film.

Abstract: In a method of forming a metal line of a semiconductor device, a dielectric film is formed on a semiconductor substrate. A plurality of parallel photoresist patterns are formed over the entire structure including the dielectric film. A spacer is formed on sidewalls of the photoresist patterns. The dielectric film is exposed by removing the photoresist patterns. Damascene patterns are formed by etching the exposed dielectric film. The spacer is removed. Metal material is formed over the entire structure including the damascene patterns and polishing the metal material, thereby forming a metal line.

Abstract: A semiconductor device and/or a method for manufacturing a semiconductor device. A method may include at least one of the following: Forming a first oxide layer on a silicon substrate. Depositing a polysilicon layer on the first oxide layer. Forming a pattern on the polysilicon layer and the first oxide layer to expose a portion of the silicon substrate forming a polysilicon layer pattern and a first oxide layer pattern. Forming a second oxide layer on the entire surface of the silicon substrate. Forming a pattern on the second oxide layer to expose a portion of the silicon substrate. Growing a silicon on the exposed silicon substrate to form a silicon epitaxial layer. Removing the second oxide layer formed on the polysilicon layer pattern.

Abstract: A conductor pattern including a gate electrode and an auxiliary pattern spaced apart by a narrow gap is formed on a substrate, an insulating film for a gate insulating film is formed so as to cover the same, a resist film is formed thereon, and the resist film is exposed from a back surface side of the substrate. In the exposure, the conductor pattern functions as a mask, but a resolution is reduced so that the resist film cannot resolve the dimension of the gap, whereby a portion corresponding to the gap is not formed in the resist pattern after development. By the lift-off method using the resist pattern, the source and drain electrodes aligned with the gate electrode are formed. The shape of the source and drain electrodes can be adjusted to an arbitrary shape by adjusting the shape of the auxiliary pattern.

Abstract: A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 ?m or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.

Abstract: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.

Abstract: A technology is provided which allows, in a coupling portion obtained by burying a conductive material within a coupling hole bored in an insulating film, the removal of a natural oxide film on the surface of a silicide layer which is present at the bottom portion of the coupling hole. A coupling hole is bored in an interlayer insulating film (first and second insulating films) to expose the surface of a nickel silicide layer at the bottom portion of the coupling hole. Then, reduction gases including a HF gas and a NH3 gas is supplied to the principal surface of a semiconductor wafer to form a product by a reduction reaction, and remove the natural oxide film on the surface of the nickel silicide layer. At this time, the flow rate ratio (HF/NH3 gas flow rate ratio) between the NF gas and the NH3 gas is adjusted to be more than 1 and not more than 5. Preferably, the temperature of the semiconductor wafer is adjusted to be not more than 30° C. Thereafter, a heating process is performed at 400° C.

Abstract: Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

Abstract: As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO2 is formed on a wing formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

Abstract: Techniques to improve characteristics of processed semiconductor substrates are described, including cleaning a substrate using a preclean process, the substrate comprising a dielectric region and a conductive region, introducing a hydroquinone to the substrate after cleaning the substrate using the preclean operation, and forming a capping layer over the conductive region of the substrate after introducing the hydroquinone.

Abstract: A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.

Abstract: To obtain a conductive metal film having superior step coverage, adhesiveness, and high productivity. A conductive metal film or metal oxidized film suitable as a capacitor electrode is formed on a substrate by performing an excited-gas supplying step after a source gas supplying step. In the source gas supplying step, gas obtained by vaporizing an organic source is supplied to the substrate, and the gas thus supplied is allowed to be adsorbed on the substrate. In the excited-gas supplying step, oxygen or nitrogen containing gas excited by plasma is supplied to the substrate to decompose the source adsorbed on the substrate, thus forming a film. An initial film-forming stop is a step of forming the film by repeating the source gas supplying step and the excited-gas supplying step once or multiple times. A desired thickness can be obtained by one step of the initial film-forming step.

Abstract: Cyclical methods of depositing a ruthenium layer on a substrate are provided. In one process, initial or incubation cycles include supplying alternately and/or simultaneously a ruthenium precursor and an oxygen-source gas to deposit ruthenium oxide on the substrate. The ruthenium oxide deposited on the substrate is reduced to ruthenium, thereby forming a ruthenium layer. The oxygen-source gas may be oxygen gas (O2). The ruthenium oxide may be reduced by supplying a reducing agent, such as ammonia (NH3) gas. The methods provide a ruthenium layer having good adherence to an underlying high dielectric layer while providing good step coverage over structures on the substrate. After nucleation, subsequent deposition cycles can be altered to optimize speed and/or conformality rather than adherence.

Abstract: A manufacturing method of an electro line for a liquid crystal display device includes depositing a barrier layer made of a conducting material on a substrate, depositing a copper layer (Cu) on the barrier layer, wet-etching the Cu layer using a first etchant, and dry-etching the barrier layer using a second etchant using the wet-etched Cu layer as an etch mask.

Abstract: The present invention relates to a process for selectively coating certain areas of a composite surface with a conductive film, to a process for fabricating interconnects in microelectronics, and to processes and methods for fabricating integrated circuits, and more particularly to the formation of networks of metal interconnects, and also to processes and methods for fabricating microsystems and connectors.

Abstract: The present disclosure relates to the fields of microchips with microfluidic optical chambers with enhanced Raman surfaces for multiplexed optical spectroscopy. Embodiments of the present invention allow for ultra small sample volume, as well as high detection speed and throughput, as compared to conventional cuvettes or devices used in optical spectroscopy. Particular embodiments relate to scientific and medical research, the diagnosis of diseases such as cancer, cardiovascular disease, diabetes, etc., and specifically to the detection of biomarkers and determination of protein activity with relevant scientific and medical applications.

Abstract: A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact opening in the barrier metal layer and the insulating layer over a third diffusion region to expose the semiconductor substrate; forming an aluminum layer on the barrier metal layer and the insulating layer and in the first, second and third contact openings; and patterning the aluminum layer to form the ohmic contact over the first diffusion region and the zener zap diode over the second and third diffusion regions.

Abstract: A method for fabricating a dual layer gate electrode having a polysilicon layer and a workfunction metal layer comprises depositing a layer of a workfunction metal on a semiconductor substrate, depositing a layer of polysilicon on the workfunction metal layer, depositing a hard mask layer on the polysilicon layer, etching the hard mask layer to form a hard mask structure defining a gate electrode, etching the polysilicon layer to remove a portion of the polysilicon layer not protected by the hard mask structure, thereby forming a polysilicon structure beneath the hard mask structure, applying a mixture of ozone and water to exposed sidewalls of the polysilicon structure, thereby forming a silicon dioxide layer on the sidewalls, and etching the workfunction metal layer to remove a portion of the workfunction metal layer not protected by the hard mask structure, thereby forming a workfunction metal structure beneath the polysilicon structure.

Abstract: A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.

Abstract: It is possible to substantially remove a polymer residue from metal lines formed over a semiconductor device without damage to the metal lines. The disclosed method includes forming a metal layer over a lower layer. A photoresist film is formed over the metal layer, and then patterned. The metal layer is selectively etched, using the patterned photoresist film as an etch barrier, to form metal lines. A substantial portion of the photoresist film left on the metal lines is removed, leaving a polymer residue. Ultraviolet rays are irradiated onto the metal lines to degrade the polymer residue, and the residue is rinsed away.

Abstract: A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includes the steps of: (a) forming a first insulating film to cover the parts of the substrate corresponding to the first and second regions; (b) forming a first thin film on the first insulating film, the first thin film having a relatively higher etching rate than the first insulating film in plasma etching using a halogen gas; and (c) removing a part of the first thin film corresponding to the first region by the plasma etching using a mask covering the second region and modifying a part of the first insulating film corresponding to the first region.

Abstract: Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Abstract: In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.

Abstract: There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on the substrate by reducing the liquefied metal ion source that is adsorbed on the substrate with a liquefied reducing agent; and rinsing the substrate to remove the remaining liquefied reducing agent and any reaction residual.

Abstract: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore, a part or all of the metal hard mask 107 is removed before the formation of TaN and Cu layers in the wiring groove 111. This enables a reduction in possible damage, which may increase the dielectric constant of the surface of low-dielectric-constant film, and thus in possible inter-wire leakage current. As a result, a reliable semiconductor device can be provided.

Abstract: In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed.

Abstract: A method of manufacturing a semiconductor device comprises carrying a substrate into a processing chamber, forming a film containing ruthenium on the substrate by supplying a material gas into the processing chamber, carrying the film-formed substrate out of the processing chamber; and cleaning an inside of the processing chamber by executing, alternately plural times, removing deposits containing ruthenium deposited in the processing chamber by supplying a cleaning gas whose molecule has a fluorine atom or a chlorine atom into the processing chamber and exposing surfaces of the deposits by removing a by-product generated so as to cover the surfaces of the deposits in removing the deposits.

Abstract: A method for forming a semiconductor device and selectively forming a salicide layer is described. In one embodiment, the method includes depositing a metal layer over a semiconductor substrate having a first area and a second area, wherein the first area and the second area include silicon, removing the metal layer over the second gate electrode, and reacting the metal layer with the first area to form a salicide layer over the first area. In one embodiment, the first area and the second area include a first gate electrode and a second gate electrode, respectively.

Abstract: An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder.

Abstract: Provided is a method of depositing a noble metal layer using an oxidation-reduction reaction. The method includes flowing a noble metal source gas, an oxidizing gas, and a reducing gas into a reaction chamber; and generating plasma in the reaction chamber to form a noble metal layer or a noble metal oxide layer on a bottom structure.

Abstract: A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one load lock chamber, at least one first physical vapor deposition (PVD) chamber configured to deposit a first material layer on a substrate, and at least one second PVD chamber for in-situ deposition of a second material layer over the first material layer within the same substrate processing system without breaking the vacuum or taking the substrate out of the substrate processing system to prevent surface contamination, oxidation, etc. The substrate processing system is configured to provide high throughput and compact footprint for in-situ sputtering of different material layers in designated PVD chambers.

Abstract: A method for forming a seed layer for damascene copper wiring is provided. The method comprises the step of forming a seed layer, during damascene copper wiring formation, using an electroless plating solution comprising a water-soluble nitrogen-containing polymer and glyoxylic acid as a reducing agent, wherein the weight-average molecular weight (Mw) of the water-soluble nitrogen-containing polymer is 1,000 to less than 100,000. Preferably, the electroless plating solution further comprises phosphinic acid.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

Abstract: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides.

Abstract: This invention relates to photosensitive organometallic compounds which are used in the production of metal deposits. In particular, this invention relates to photosensitive organometallic compounds such as bis-(perfluoropropyl)-1,5-cyclooctadiene platinum (II) (i.e. (C3F7)2PtC8H12) which on exposure to UV radiation and then a reduction process forms a platinum metal deposit such as a substantially continuous thin ‘sheet-like’ film or a substantially narrow line which is capable of electrical conduction.

Abstract: In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of ?-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of ?-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.