Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.

Abstract: Methods for precleaning native oxides or other contaminants from a surface of a substrate prior to forming a metal silicide layer on the substrate. In one embodiment, a method for removing native oxides from a substrate includes transferring a substrate having an oxide layer disposed thereon into a processing chamber, performing a pretreatment process on the substrate by supplying a pretreatment gas mixture into the processing chamber, performing an oxide removal process on the substrate by supplying a cleaning gas mixture into the processing chamber, wherein the cleaning gas mixture includes at least an ammonium gas and a nitrogen trifluoride, and performing a post treatment process on the cleaned substrate by supplying a post treatment gas mixture into the processing chamber.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step.

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract: A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.

Abstract: Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate.

Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is eptiaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.

Abstract: Formation of a semiconductor device with NiGe or NiSiGe and with reduced consumption of underlying Ge or SiGe is provided. Embodiments include co-sputtering nickel (Ni) and germanium (Ge), forming a first Ni/Ge layer on a Ge or silicon germanium (SiGe) active layer, depositing titanium (Ti) on the first Ni/Ge or Ni/Si/Ge layer, forming a Ti intermediate layer, co-sputtering Ni and Ge on the Ti intermediate layer, forming a second Ni/Ge layer, and performing a rapid thermal anneal (RTA) process.

Abstract: Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.

Abstract: The present invention relates to a semiconductor component which comprises at least one electric contact surface for the electric contacting of a semiconductor region (1) with a metal material (3). To this end, the electric contact surface is configured by a surface of a semiconductor layer that is structured in terms of the depth thereof and preferably silicidated. By configuring a three-dimensional surface topography of the semiconductor layer, an enlargement of the electric contact surface is achieved, without enlarging the surface required for the semiconductor component and without the use of additional materials. In this way, the invention can advantageously be used to reduce parasitic contact resistance in semiconductor components which are produced using standard CMOS processes.

Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract: A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract: A capacitive sensor device for measuring radiation. The device includes two sensor regions and top plate structure. The sensor regions are of a material that generates electron-hole pairs when radiation strikes the material. A separation region is located between the two sensor regions. The capacitance between a sensor region and top plate is dependent upon radiation striking the sensor region. A blocking structure selectively and differentially blocks radiation having a parameter value in a range from the sensor region so as to differentially impact electron-hole pair generation of one sensor region with respect to electron-hole pair generation of the other sensor region at selected angles of incidence of the radiation.

Abstract: An MOSFET device having a Silicide layer of uniform thickness and which is substantially free of “Spotty” NiSi-type holes, and methods for its fabrication, are provided. One such method involves simultaneously depositing a metal layer (e.g. Ni) over the active and open areas of a semiconductor substrate. The depth to which some or all of the metal is transferred into the substrate is determined by thermal budget. A rapid thermal annealing process is employed to produce a NiSi layer of a uniform thickness in both the active and open areas. Upon achieving a NiSi layer of a desired thickness, the excess metal is removed from the substrate surface.

Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.

Abstract: Highly thermally stable metal silicides and methods utilizing the metal silicides in semiconductor processing are provided. The metal silicides are preferably nickel silicides formed by the reaction of nickel with substitutionally carbon-doped single crystalline silicon which has about 2 atomic % or more substitutional carbon. Unexpectedly, the metal silicides are stable to temperatures of about 900° C. and higher and their sheet resistances are substantially unaffected by exposure to high temperatures. The metal silicides are compatible with subsequent high temperature processing steps, including reflow anneals of BPSG.

Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.

Abstract: In the manufacturing steps of a power-type semiconductor device, after grinding the back surface of the semiconductor wafer, when a metal film is deposited by sputtering deposition over the back surface of the wafer in a preheated state, the wafer is contained in an annular susceptor, and processed. A radial vertical cross section of the annular shape of the susceptor has a first upper surface closer to a horizontal surface for holding a peripheral portion of the top surface of the semiconductor wafer against gravity, and a second upper surface continued to and located outside the first upper surface and closer to a vertical surface for holding a side surface of the semiconductor wafer against lateral displacement.

Abstract: The present invention is directed to a method for forming a crystalline cobalt silicide film, comprising the steps of: applying to a surface made of silicon a composition obtained by mixing a compound represented by the following formula (1A) or (1B): SinX2n+2??(1A) SimX2m??(1B) wherein each X in the formulas (1A) and (1B) is a hydrogen atom or a halogen atom, n is an integer of 1 to 10, and m is an integer of 3 to 10, or a polymer thereof with a zero-valent cobalt complex to form a coating film; heating the coated film at 550 to 900° C. so as to form a two-layer film which is composed of a first layer made of a crystalline cobalt silicide on the surface made of silicon and a second layer containing silicon atoms, oxygen atoms, carbon atoms and cobalt atoms on the first layer; and removing the second layer of the two-layer film.

Abstract: Methods for precleaning native oxides or other contaminants from a surface of a substrate prior to forming a metal silicide layer on the substrate.

Abstract: In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD.

Abstract: A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, exposing the substrate to a gas mixture while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to sublimate the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate.

Abstract: Disclosed are a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate having a lead frame, a light emitting diode mounted on the substrate, a mold member formed on the substrate and the light emitting diode, and a reflecting member having an opening portion at one side thereof and being inclined at an outer portion of the mold member.

Abstract: Embodiments of the invention generally provide methods for forming cobalt silicide. In one embodiment, a method for forming a cobalt silicide material includes exposing a substrate having a silicon-containing material to either a wet etch solution or a pre-clean plasma during a first step and then to a hydrogen plasma during a second step of a pre-clean process. The method further includes depositing a cobalt metal layer on the silicon-containing material by a CVD process, heating the substrate to form a first cobalt silicide layer comprising CoSi at the interface of the cobalt metal layer and the silicon-containing material during a first annealing process, removing any unreacted cobalt metal from the substrate during an etch process, and heating the substrate to form a second cobalt silicide layer comprising CoSi2 during a second annealing process.

Abstract: Techniques for silicide, germanide or germanosilicide formation in extremely small structures are provided. In one aspect, a method for forming a silicide, germanide or germanosilicide in a three-dimensional silicon, germanium or silicon germanium structure having extremely small dimensions is provided. The method includes the following steps. At least one element is implanted into the structure. At least one metal is deposited onto the structure. The structure is annealed to intersperse the metal within the silicon, germanium or silicon germanium to form the silicide, germanide or germanosilicide wherein the implanted element serves to prevent morphological degradation of the silicide, germanide or germanosilicide. The implanted element can include at least one of carbon, fluorine and silicon.

Abstract: Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products.

Abstract: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (210). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (230), wherein the NMOS gate structure (230) includes an NMOS gate dielectric (240) and an NMOS gate electrode (250). This method further includes forming n-type source/drain regions (710) within the substrate (210) proximate the NMOS gate structure (230), and siliciding the NMOS gate electrode (250) to form a silicided gate electrode (1110, 1210). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode (250) prior to or concurrently with siliciding.

Abstract: The method described herein involves the formation of metal silicide regions. The method may involve forming a layer of refractory metal on a structure comprising silicon, forming a layer of silicon on the layer of refractory metal and, after forming the layer of silicon, performing at least one heat treatment process to form a metal silicide region in the structure.

Abstract: A semiconductor device manufacturing method which prevents the resistance of a Ni silicide layer from increasing due to an additive element. First, a reaction control layer which contains a metallic element with an atomic number greater than Ni and does not contain Ni is formed over a silicon layer. Then, Ni is deposited over the reaction control layer and the silicon layer, reaction control layer and Ni are heat-treated to form a Ni silicide layer in the silicon layer. It is preferable that the reaction control layer be comprised of a metallic element with an atomic number greater than Ni.

Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.

Abstract: A method of forming nickel monosilicide is provided that includes providing a silicon-containing surface, and ion implanting carbon into the silicon-containing surface. A nickel-containing layer is formed on the silicon-containing surface. Alloying the nickel-containing surface and the silicon-containing surface layer to provide a nickel monosilicide. The present disclosure also provides a non-agglomerated Ni monosilicide contact that includes a carbon interstitial dopant present in a concentration ranging from 1×1019 atoms/cm3 to 1×1021 atoms/cm3.

Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Abstract: A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.

Abstract: Methods of forming a semiconductor device include providing a substrate having an area including a source and a drain region of a transistor. A nickel (Ni) metal film is formed on the substrate area including the source and the drain region. A first heat-treatment process is performed including heating the substrate including the metal film from a first temperature to a second temperature at a first ramping rate and holding the substrate including the metal film at the second temperature for a first period of time. A second heat-treatment process is then performed including heating the substrate including the metal film from a third temperature to a fourth temperature at a second ramping rate and holding the substrate at the fourth temperature for a second period of time. The fourth temperature is different from the second temperature and the second period of time is different from the first period of time.