Using Electromagnetic Radiation, E.g., Laser Radiation (epo) Patents (Class 257/E21.347)
  • Patent number: 11769852
    Abstract: A method of manufacturing a light emitting element according to certain embodiments of the present disclosure includes: scanning and irradiating a first laser light having a first irradiation intensity to a sapphire substrate along predetermined dividing lines collectively in a shape of a tessellation of a plurality of hexagonal shapes in a top view to create a plurality of first modified regions along the predetermined dividing lines; and scanning and irradiating a second laser light having a second irradiation intensity greater than the first irradiation intensity to the sapphire substrate along the predetermined dividing lines to create a plurality of second modified regions overlapping the plurality of first modified regions.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 26, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Masayuki Ibaraki, Minoru Yamamoto, Naoto Inoue, Hiroaki Tamemoto
  • Patent number: 11271119
    Abstract: A method for metallization includes providing a transparent donor substrate (34) having deposited thereon a donor film (36) including a metal with a thickness less than 2 ?m. The donor substrate is positioned in proximity to an acceptor substrate (22) including a semiconductor material with the donor film facing toward the acceptor substrate and with a gap of at least 0.1 mm between the donor film and the acceptor substrate. A train of laser pulses, having a pulse duration less than 2 ns, is directed to impinge on the donor substrate so as to cause droplets (44) of the metal to be ejected from the donor layer and land on the acceptor substrate, thereby forming a circuit trace (25) in ohmic contact with the semiconductor material.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 8, 2022
    Assignee: Orbotech Ltd.
    Inventors: Michael Zenou, Zvi Kotler
  • Patent number: 10916656
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Patent number: 10734520
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Patent number: 10475926
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Patent number: 10297479
    Abstract: Structures and methods are provided for temporarily bonding handler wafers to device wafers using bonding structures that include one or more releasable layers which are laser-ablatable using mid-wavelength infrared radiation.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John U. Knickerbocker, Cornelia Kang-I Tsang
  • Patent number: 10147609
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10114263
    Abstract: A liquid crystal display device includes a transmissive region and a reflective region. The liquid crystal display device includes a liquid crystal element, a transistor, a scan line, a signal line, and an insulating layer. A semiconductor layer of the transistor includes a channel region and a low-resistance region. A channel region overlaps with a gate with a gate insulating layer provided therebetween. The low-resistance region includes a first portion in contact with a pixel electrode of the liquid crystal element and a second portion in contact with a side surface of an opening portion in the insulating layer. The first portion of the low-resistance region is positioned in the transmissive region or the reflective region. The reflective region includes a layer that reflects visible light. The layer that reflects visible light includes a portion positioned between the scan line or the signal line and a liquid crystal layer.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kubota, Koji Kusunoki, Kensuke Yoshizumi
  • Patent number: 10062781
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Patent number: 9853155
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok
  • Patent number: 9698053
    Abstract: This work provides a new approach for epitaxial liftoff. Instead of using a sacrificial layer that is selectively etched chemically, the sacrificial layer selectively absorbs light that is not absorbed by other parts of the structure. Under sufficiently intense illumination with such light, the sacrificial layer is mechanically weakened, melted and/or destroyed, thereby enabling epitaxial liftoff. The perimeter of the semiconductor region to be released is defined (partially or completely) by lateral patterning, and the part to be released is also adhered to a support member prior to laser irradiation. The end result is a semiconductor region removed from its substrate and adhered to the support member.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 4, 2017
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Garrett J. Hayes, Bruce M. Clemens
  • Patent number: 9680049
    Abstract: In at least one embodiment, a method is designed to produce optoelectronic semiconductor chips. A carrier assembly, which is a sapphire wafer, is produced. A semiconductor layer sequence is applied to the carrier assembly. The carrier assembly and the semiconductor layer sequence are divided into the individual semiconductor chips. The dividing is implemented by producing a multiplicity of selectively etchable material modifications in the carrier assembly in separation region(s) by focused, pulsed laser radiation. The laser radiation has a wavelength at which the carrier assembly is transparent. The dividing includes wet chemically etching the material modifications, such that the carrier assembly is singulated into individual carriers for the semiconductor chips solely by the wet chemical etching or in combination with a further material removal method.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: June 13, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andreas Plöβl
  • Patent number: 9620355
    Abstract: A wafer processing method includes a wafer holding step of holding a wafer having devices formed on the front side, a protective film forming step of forming a water-soluble protective film on the front side of the wafer, a laser beam applying step of applying a laser beam to the wafer along streets, a cleaning step of cleaning the wafer to then remove the protective film, and a foreign matter removing step of removing foreign matter from the wafer when a predetermined period of time has elapsed after cleaning. This period of time is set as a period of time until a phosphorus containing reaction product produced at a laser processed portion is evaporated to react with water in the air, thereby producing the foreign matter containing phosphorus on bumps formed on each device.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: April 11, 2017
    Assignee: Disco Corporation
    Inventors: Senichi Ryo, Hirokazu Matsumoto, Toshiyuki Yoshikawa, Yukinobu Ohura
  • Patent number: 9290858
    Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 22, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Stephen Moffatt
  • Patent number: 9276129
    Abstract: An object of an embodiment of the present invention is to manufacture a highly-reliable semiconductor device comprising a transistor including an oxide semiconductor, in which change of electrical characteristics is small. In the transistor including an oxide semiconductor, oxygen-excess silicon oxide (SiOX (X>2)) is used for a base insulating layer of a top-gate structure or for a protective insulating layer of a bottom-gate structure. By using the oxygen-excess silicon oxide, oxygen is discharged from the insulating layer, and oxygen deficiency of an oxide semiconductor layer and the interface state density between the oxide semiconductor layer and the base insulating layer or the protective insulating layer can be reduced, so that the highly-reliable semiconductor device in which change of electrical characteristics is small can be manufactured.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: March 1, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Yuta Endo
  • Patent number: 9029987
    Abstract: While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed 1 is irradiated with laser light L, so as to form modified regions 17, 27, 37, 47 extending along lines to cut 5 and aligning in the thickness direction in the object 1. Here, modified regions 17 are formed such that modified region formed parts 17a and modified region unformed parts 17b alternate along the lines, and modified regions 47 are formed such that modified region formed parts 47a and modified region unformed parts 47b alternate along the lines. This can inhibit formed modified regions 7 from lowering the strengths on the rear face 21 side and front face 3 side of chips obtained by cutting. On the other hand, modified regions 27, 37 located between the modified regions 17, 47 are formed continuously from one end side of the lines 5 to the other end side thereof, whereby the cuttability of the object 1 can be secured reliably.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: May 12, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Aiko Nakagawa, Takeshi Sakamoto
  • Patent number: 9012338
    Abstract: In the present invention, At least one row of lens arrays, in which a plurality of lenses are arranged in a direction intersecting with the conveying direction of a substrate to correspond to the plurality of TFT forming areas set in a matrix on the substrate, is shifted in the direction intersecting with the conveying direction of the substrate, to thereby align the lenses in the lens array with the TFT forming areas on the substrate based on the alignment reference position. The laser beams are irradiated onto the lens array when the substrate moves and the TFT forming areas reach the underneath of the corresponding lenses of the lens array, and the laser beams are focused by the plurality of lenses to anneal the amorphous silicon film in each TFT forming area.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: April 21, 2015
    Assignee: V Technology Co., Ltd.
    Inventors: Koichi Kajiyama, Michinobu Mizumura
  • Patent number: 9012309
    Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 21, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung
  • Patent number: 8999865
    Abstract: A laser annealing apparatus carries out an annealing treatment an amorphous silicon film on a TFT substrate. The apparatus includes: a mask having a plurality of apertures; a microlens substrate having a plurality of microlenses arranged on a surface thereof and configured to focus the plurality of laser beams Lb, that have passed through the respective apertures of the mask, onto the TFT substrate to apply a predetermined energy to the amorphous silicon film; a pair of guides each having a semi-cylindrical shape and disposed along both sides across the microlens substrate so that the axes of the guides are parallel to each other and that the tips of the guides protrude from the positions of tips of the microlenses toward the TFT substrate; and a film that is provided in a tensioned state between the pair of guides so as to be movable and that transmits a laser beam.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: April 7, 2015
    Assignee: V Technology Co., Ltd.
    Inventors: Michinobu Mizumura, Yuji Saito
  • Patent number: 8987829
    Abstract: A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Shimooka, Takashi Izumida, Hiroki Okamoto
  • Patent number: 8969752
    Abstract: The present invention provides a laser processing method comprising the steps of attaching a protective tape 25 to a front face 3 of a wafer 1a, irradiating a substrate 15 with laser light L while employing a rear face of the wafer 1a as a laser light entrance surface and locating a light-converging point P within the substrate 15 so as to form a molten processed region 13 due to multiphoton absorption, causing the molten processed region 13 to form a cutting start region 8 inside by a predetermined distance from the laser light entrance surface along a line 5 along which the object is intended to be cut in the wafer 1a, attaching an expandable tape 23 to the rear face 21 of the wafer 1a, and expanding the expandable tape 23 so as to separate a plurality of chip parts 24 produced upon cutting the wafer 1a from the cutting start region 8 acting as a start point from each other.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: March 3, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kenshi Fukumitsu, Fumitsugu Fukuyo, Naoki Uchiyama
  • Patent number: 8969134
    Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
  • Patent number: 8969220
    Abstract: Examples of methods and systems for laser processing of materials are disclosed. Methods and systems for singulation of a wafer comprising a coated substrate can utilize a laser outputting light that has a wavelength that is transparent to the wafer substrate but which may not be transparent to the coating layer(s). Using techniques for managing fluence and focal condition of the laser beam, the coating layer(s) and the substrate material can be processed through ablation and internal modification, respectively. The internal modification can result in die separation.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 3, 2015
    Assignee: IMRA America, Inc.
    Inventors: Alan Y. Arai, Gyu Cheon Cho, Jingzhou Xu
  • Patent number: 8963197
    Abstract: An LED package includes a package body having a well formed in its upper surface, where the well is configured to receive a light emitting chip. An optical lens is disposed above the package body and includes a hollow dome structure located above and encompassing the lateral extent of the light emitting chip within the well of the package body. In one implementation, the package body and the optical lens collectively include at least one protrusion and concave, where the protrusion is aligned with the concave so that the optical lens mates with the package body, thereby causing the optical lens to self align with the package body. In another implementation, a protruding inner portion of the upper surface of the package body mates with the hollow dome structure, achieving a similar purpose. Consequently, generation of an eccentric fault between the optical lens and the package body is prevented.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Myung Soo Han, Seung Ho Jang, Won Seok Choi
  • Patent number: 8937020
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
  • Patent number: 8928052
    Abstract: An optoelectronic semiconductor chip has a semiconductor layer sequence having an active layer that generates radiation between a layer of a first conductivity type and a layer of a second conductivity type. The layer of the first conductivity type is adjacent to a front side of the semiconductor layer sequence. The semiconductor layer sequence contains at least one cutout extending from a rear side, lying opposite the front side, of the semiconductor layer sequence through the active layer to the layer of the first conductivity type. The layer of the first conductivity type is electrically connected through the cutout by means of a first electrical connection layer which covers the rear side of the semiconductor layer sequence at least in places.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 6, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Engl, Lutz Hoeppel, Patrick Rode, Matthias Sabathil
  • Patent number: 8927348
    Abstract: Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer (30) so as to a main surface (20) of a substrate (2), a masking step of forming a protective film on the semiconductor layer (30), a semiconductor layer removal step of removing the protective film and the semiconductor layer (30) by laser irradiation to expose the substrate (2), a grinding step of reducing the thickness of the substrate (2), a polishing step of polishing the substrate (2), a laser processing step of providing processing marks to the inside of the substrate (2), a division step of creating a plurality of light-emitting devices (1) while forming a division surface of the substrate (2) to have a rough surface.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Susumu Sugano, Hisayuki Miki, Hironao Shinohara
  • Patent number: 8906725
    Abstract: A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 9, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Stephen Moffatt
  • Patent number: 8900715
    Abstract: A semiconductor device includes a wafer having a first surface opposite a second surface, and at least one laser irradiated region between the first and second surfaces. The laser irradiated region includes a laser-induced stress that is configured to minimize curvature of at least one of the first and second surfaces.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies AG
    Inventor: Horst Theuss
  • Patent number: 8883656
    Abstract: High throughput systems and processes for recrystallizing thin film semiconductors that have been deposited at low temperatures on a substrate are provided. A thin film semiconductor workpiece is irradiated with a laser beam to melt and recrystallize target areas of the surface exposed to the laser beam. The laser beam is shaped into one or more beamlets using patterning masks. The mask patterns have suitable dimensions and orientations to pattern the laser beam radiation so that the areas targeted by the beamlets have dimensions and orientations that are conducive to semiconductor recrystallization. The workpiece is mechanically translated along linear paths relative to the laser beam to process the entire surface of the work piece at high speeds. Position sensitive triggering of a laser can be used to generate laser beam pulses to melt and recrystallize semiconductor material at precise locations on the surface of the workpiece while it is translated on a motorized stage.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: November 11, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8884407
    Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Michael Sternad, Rainer Pelzer
  • Patent number: 8877658
    Abstract: Methods for performing directed self-assembly (DSA) of block copolymer (BCP) material on a substrate are disclosed. The BCP is disposed over a patterned neutral layer made from a random copolymer. The BCP is annealed with a laser to induce the directed self-assembly. The scan type may include single scan, multiple scan, or multiple scan with overlap. A variety of power settings and dwell times may be used within a single wafer to achieve multiple heating conditions within a single wafer.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Kenji Yoshimoto
  • Patent number: 8871649
    Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignees: GLOBALFOUNDRIES Inc., Renesas Electronics Corporation, International Business Machines Corporation
    Inventors: Linus Jang, Yoshinori Matsui, Chiahsun Tseng
  • Patent number: 8865568
    Abstract: Fractures (17a, 17b) are generated from modified regions (7a, 7b) to front and rear faces (12a, 12b) of a object to be processed (1), respectively, while an unmodified region (2) is interposed between the modified regions (7a, 7b). This can prevent fractures from continuously advancing in the thickness direction of a silicon substrate (12) when forming a plurality of rows of modified regions (7). By generating a stress in the object (1), the fractures (17a, 17b) are connected to each other in the unmodified region (2), so as to cut the object (1). This can prevent fractures from meandering in the rear face (12b) of the object (1) and so forth, whereby the object (1) can be cut accurately along a line to cut the object (5).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: October 21, 2014
    Assignee: Hamamatsu Photonics K.K
    Inventors: Takeshi Sakamoto, Aiko Nakagawa
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8859331
    Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Dong Lim Kim, Joohye Jung, You Seung Rim
  • Patent number: 8828260
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8828891
    Abstract: For modulating laser light for forming a modified region SD3 at an intermediate position between a position closer to a rear face 21 and a position closer to a front face 3 with respect to an object 1, a quality pattern J having a first brightness region extending in a direction substantially orthogonal to a line 5 and second brightness regions located on both sides of the first brightness region in the extending direction of the line 5 is used. After forming modified regions SD1, SD2 at positions closer to the rear face 21 but before forming modified regions SD4, SD5 at positions closer to the rear face 21 while using the front face 3 as a laser light entrance surface, the modified region SD3 is formed at the intermediate position by irradiation with laser light modulated according to a modulation pattern including the quality pattern J.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Takeshi Sakamoto
  • Patent number: 8822255
    Abstract: A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 2, 2014
    Assignee: Ulvac, Inc.
    Inventors: Yoshiaki Yamamoto, Hitoshi Ikeda, Tomoki Ohnishi, Kouichi Tamagawa
  • Patent number: 8815719
    Abstract: A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then annealed to completely dissociate and activate the boron clusters. The annealing may take place by melting the implanted regions or by a sub-melt annealing process.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: August 26, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jiping Li, Aaron Muir Hunter, Bruce E. Adams, Theodore Moffitt, Stephen Moffatt
  • Patent number: 8810030
    Abstract: A MEMS device (20) with stress isolation includes elements (28, 30, 32) formed in a first structural layer (24) and elements (68, 70) formed in a second structural layer (26), with the layer (26) being spaced apart from the first structural layer (24). Fabrication methodology (80) entails forming (92, 94, 104) junctions (72, 74) between the layers (24, 26). The junctions (72, 74) connect corresponding elements (30, 32) of the first layer (24) with elements (68, 70) of the second layer (26). The fabrication methodology (80) further entails releasing the structural layers (24, 26) from an underlying substrate (22) so that all of the elements (30, 32, 68, 70) are suspended above the substrate (22) of the MEMS device (20), wherein attachment of the elements (30, 32, 68, 70) with the substrate (22) occurs only at a central area (46) of the substrate (22).
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: August 19, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Aaron A. Geisberger
  • Patent number: 8809192
    Abstract: A method for deposition of at least one electrically conducting film on a substrate, wherein the method includes the steps of: selecting a layer of a film material, wherein the layer includes a mask on a front side, and wherein the layer and the mask are one piece; positioning the front side of the layer upon the substrate; applying at least one laser pulse onto a back side of the layer, so as to melt and to vaporize at least parts of the layer such that melt droplets are propelled toward and deposited upon the substrate; and forming the film, wherein at least one slot of the mask limits the distribution of the melt droplets.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: August 19, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Dietrich Bertram, Jochen Hugo Stollenwerk, Johannes Krijne, Holger Schwab, Edward Willem Albert Young, Jeroen Henri Antoine Maria Van Buul, Andres Gasser, Konrad Wissenbach, Christian Vedder, Norbert Pirch
  • Patent number: 8802580
    Abstract: Crystallization of thin films using pulsed irradiation The method includes continuously irradiating a film having an x-axis and a y-axis, in a first scan in the x-direction of the film with a plurality of line beam laser pulses to form a first set of irradiated regions, translating the film a distance in the y-direction of the film, wherein the distance is less than the length of the line beam, and continuously irradiating the film in a second scan in the negative x-direction of the film with a sequence of line beam laser pulses to form a second set of irradiated regions, wherein each of the second set of irradiated regions overlaps with a portion of the first set of irradiated regions, and wherein each of the first and the second set of irradiated regions upon cooling forms one or more crystallized regions.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: August 12, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8803026
    Abstract: Provided are: a table on which a workpiece is placed, a laser oscillator emitting a laser beam; a light-guide optical system deflecting the beam emitted from the oscillator; a cylindrical extensible bellows surrounding an optical path of the beam after the light-guide optical system deflects the beam; a bend mirror moving in an axial direction of the bellows while extending/contracting the bellows and deflecting the beam having passed through the bellows toward the table; a machining head irradiating the workpiece with the beam deflected by the mirror; an abnormality detector including a beam-sensor light-emitting unit emitting a beam advancing parallel with an axis of the bellows and a beam-sensor light-receiving unit measuring the amount of received light of the beam; and a control device bringing down the laser oscillator when the amount of received light of the beam in the beam-sensor light-receiving unit falls below a first threshold.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: August 12, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shigeru Yokoi
  • Patent number: 8796131
    Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Edward E. Jones, Sharad N. Yedave, Ying Tang, Barry Lewis Chambers, Robert Kaim, Joseph D. Sweeney, Oleg Byl, Peng Zou
  • Patent number: 8790997
    Abstract: While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed 1 is irradiated with laser light L, so as to form modified regions 17, 27, 37, 47 extending along lines to cut 5 and aligning in the thickness direction in the object 1. Here, modified regions 17 are formed such that modified region formed parts 17a and modified region unformed parts 17b alternate along the lines, and modified regions 47 are formed such that modified region formed parts 47a and modified region unformed parts 47b alternate along the lines. This can inhibit formed modified regions 7 from lowering the strengths on the rear face 21 side and front face 3 side of chips obtained by cutting. On the other hand, modified regions 27, 37 located between the modified regions 17, 47 are formed continuously from one end side of the lines 5 to the other end side thereof, whereby the cuttability of the object 1 can be secured reliably.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 29, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Aiko Nakagawa, Takeshi Sakamoto
  • Patent number: 8790969
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondo, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8778780
    Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: July 15, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Trung-Tri Doan, Chen-Fu Chu, Hao-Chun Cheng, Feng-Hsu Fan
  • Patent number: 8772173
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-kwan Yu, Dong-suk Shin, Pan-kwi Park, Ki-eun Kim
  • Patent number: 8759951
    Abstract: The present invention provides a method for selectively transferring elements such as monocrystalline Si thin films or elements made of monocrystalline Si from a base substrate (100) onto an insulating substrate without the use of an intermediate substrate. The base substrate (first substrate) (100) in which the elements are formed is selectively irradiated with a laser having a multiphoton absorption wavelength. Thus, elements to be transferred out of the elements and corresponding thin films on the base substrate (100) are transferred onto a transfer destination substrate (second substrate) (200).
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 24, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani