Field-effect Controlled Bipolar-type Transi Stor, E.g., Insulated Gate Bipolar Transistor (igbt) (epo) Patents (Class 257/E21.382)
  • Patent number: 10679857
    Abstract: A semiconductor device and method is disclosed. In one example, the method for forming a semiconductor device includes forming a trench extending from a front side surface of a semiconductor substrate into the semiconductor substrate. The method includes forming of material to be structured inside the trench. Material to be structured is irradiated with a tilted reactive ion beam at a non-orthogonal angle with respect to the front side surface such that an undesired portion of the material to be structured is removed due to the irradiation with the tilted reactive ion beam while an irradiation of another portion of the material to be structured is masked by an edge of the trench.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 10217847
    Abstract: A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 26, 2019
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok
  • Patent number: 9882036
    Abstract: A semiconductor device includes first and second electrodes and a silicon carbide layer located between the first and second electrodes. A plurality of gate electrodes is interposed between the first electrode and the silicon carbide layer and extends in a first direction. The silicon carbide layer includes a plurality of spaced apart openings having sidewalls and a base which extend inwardly between the gate electrodes, a first region containing a second conductivity type impurity extending around and under the openings, and a second region containing a second conductivity type impurity interposed between the portion of the first region extending under the base of the openings. The concentration of the second conductivity type impurity is greater in the second region than in the first region. The silicon carbide layer includes a third region containing a first conductivity type impurity extending inwardly of the first region from the sidewall of the openings.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: January 30, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takuma Suzuki
  • Patent number: 9520433
    Abstract: A method includes forming a deep trench isolation structure on a substrate, the substrate having a back surface opposite to a front surface, the deep trench isolation structure opening toward the front surface. An oxide layer is formed on the front surface of the substrate and sidewalls and bottom of the deep trench isolation structure. The oxide layer on the front surface of the substrate is removed. A portion of the substrate at the opening of the deep trench isolation structure is removed and an epitaxial layer is formed on the substrate.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hung Chen, Dun-Nian Yaung, Jen-Cheng Liu, Alexander Kalnitsky, Wen-De Wang
  • Patent number: 9018049
    Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: April 28, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Guangran Pan
  • Patent number: 9000519
    Abstract: An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 8962397
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite
  • Patent number: 8921888
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yuan-Hsiang Chang, Sung-Bin Lin
  • Patent number: 8896021
    Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chung-I Huang, Pao-An Chang, Ming-Tsung Lee
  • Patent number: 8890169
    Abstract: On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n?-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: November 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Norifumi Kameshiro, Haruka Shimizu
  • Patent number: 8878594
    Abstract: An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Giuseppe Patti
  • Patent number: 8872222
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8853009
    Abstract: In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove. In this way, it is possible to ensure a reverse breakdown voltage and reduce a leakage current when a reverse bias applied, even in a manufacturing method including a process of manufacturing a diffusion layer formed by forming a tapered groove and performing ion implantation and an annealing process for the side surface of the tapered groove as the separation layer for bending the termination of a reverse breakdown voltage pn junction to extend to the surface.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: October 7, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Haruo Nakazawa
  • Patent number: 8809130
    Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: August 19, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
  • Patent number: 8803276
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
  • Patent number: 8779465
    Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: July 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean-Michel Reynes, Philippe Lance, Evgueniy Stefanov, Yann Weber
  • Patent number: 8772868
    Abstract: A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: July 8, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Hamza Yilmaz, James Pan, Rodney S. Ridley, Sr.
  • Patent number: 8748236
    Abstract: A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 10, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Atsushi Tanida
  • Patent number: 8729599
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: May 20, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yuan-Hsiang Chang, Sung-Bin Lin
  • Patent number: 8728923
    Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 20, 2014
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Tetsuji Kondou, Kazuhiko Sugiura, Nobuyuki Kato
  • Patent number: 8722487
    Abstract: A semiconductor device, including a silicon substrate having a first major surface and a second major surface, a front surface device structure formed in a region of the first major surface, and a rear electrode formed in a region of the second major surface. The rear electrode includes, as a first layer thereof, an aluminum silicon film that is formed by evaporating or sputtering aluminum-silicon onto the second major surface, the aluminum silicon film having a silicon concentration of at least 2 percent by weight and a thickness of less than 0.3 ?m.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: May 13, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kenichi Kazama, Tsunehiro Nakajima, Koji Sasaki, Akio Shimizu, Takashi Hayashi, Hiroki Wakimoto
  • Patent number: 8716747
    Abstract: A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: May 6, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jun Saito, Sachiko Aoi, Takahide Sugiyama
  • Patent number: 8710510
    Abstract: An insulated gate bipolar transistor (IGBT) includes a substrate having a first conductivity type, a drift layer having a second conductivity type opposite the first conductivity type, and a well region in the drift layer and having the first conductivity type. An epitaxial channel adjustment layer is on the drift layer and has the second conductivity type. An emitter region extends from a surface of the epitaxial channel adjustment layer through the epitaxial channel adjustment layer and into the well region. The emitter region has the second conductivity type and at least partially defines a channel region in the well region adjacent to the emitter region. A gate oxide layer is on the channel region, and a gate is on the gate oxide layer. Related methods are also disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: April 29, 2014
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Sei-Hyung Ryu, Charlotte Jonas, Anant K. Agarwal
  • Patent number: 8692244
    Abstract: A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoto Kaguchi, Norihisa Asano, Katsumi Sato
  • Publication number: 20140061721
    Abstract: An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Lin Chan, Shyi-Yuan Wu, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8659104
    Abstract: A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 25, 2014
    Assignee: NXP B.V.
    Inventors: Gilberto Curatola, Victor Zieren, Anco Heringa
  • Patent number: 8633510
    Abstract: The invention of the present application provides an IE-type trench IGBT. In the IE-type trench IGBT, each of linear unit cell areas that configure a cell area is comprised principally of linear active and inactive cell areas. The linear active cell area is divided into an active section having an emitter region and an inactive section as seen in its longitudinal direction.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Matsuura, Yoshito Nakazawa
  • Patent number: 8610131
    Abstract: An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm?3 or more.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 17, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Misako Honaga, Toru Hiyoshi
  • Patent number: 8603885
    Abstract: Bipolar transistors with tailored response curves, as well as fabrication methods for bipolar transistors and design structures for BiCMOS integrated circuits. The bipolar transistor includes a first section of a collector region implanted with a first dopant concentration and a second section of the collector region implanted with a second dopant concentration that is higher than the first dopant concentration. A first emitter is formed in vertical alignment with the first section of the collector region. A second emitter is formed in vertical alignment with the second section of the collector region.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ramana M. Malladi, Kim M. Newton
  • Patent number: 8597993
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad
  • Patent number: 8586442
    Abstract: A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 19, 2013
    Assignee: Macronix International Co. Ltd.
    Inventors: Yu-Hsien Chin, Chih-Chia Hsu, Yin-Fu Huang
  • Publication number: 20130299871
    Abstract: Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Inventors: Anton MAUDER, Eric GRAETZ
  • Patent number: 8581339
    Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: November 12, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Wei Chang, Ching-Lin Chan, Chin-Shien Lu, Ming-Tung Lee, Shuo-Lun Tu
  • Publication number: 20130256749
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William F. Clark, JR., Robert J. Gauthier, JR., Junjun Li
  • Publication number: 20130221404
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shin-Chin Lien
  • Patent number: 8507327
    Abstract: Cutting work is performed on an n-semiconductor substrate (1) with an inverted trapezoid-shaped dicing blade to form grooves to be a second side walls (7). Bottom portions of the grooves are contacted with a p-diffusion layer (4) which is formed on a first principal plane (2) (front face) of the n-semiconductor substrate (1), so that the p-diffusion layer (4) is not cut. Then in the second side walls (7), a p-isolation layer (9) connected to a p-collector layer (8) and the p-diffusion layer (4) is formed. Since the p-diffusion layer (4) is not cut, a glass support substrate for supporting a wafer, and expensive adhesive, are not required, and therefore the p-isolation layer (4) can be formed at low cost.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: August 13, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Tsukamoto, Kazuo Shimoyama
  • Publication number: 20130200427
    Abstract: A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.
    Type: Application
    Filed: July 16, 2012
    Publication date: August 8, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-su Jeong, Jai-kwang Shin, Nam-young Lee, Ji-hoon Lee, Min-kwon Cho, Yong-cheol Choi, Hyuk-soon Choi
  • Patent number: 8501548
    Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.).
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 6, 2013
    Assignee: ABB Technology AG
    Inventors: Jan Vobecky, Munaf Rahimo
  • Patent number: 8487343
    Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Junichi Sakano, Kenji Hara
  • Patent number: 8482030
    Abstract: A trench gate IGBT designed to reduce on-state voltage while maintaining the withstand voltage, including a first drift layer formed on a first main surface of a buffer layer, a second drift layer of the first conductivity type formed on said first drift layer, a base layer of a second conductivity type formed on the second drift layer, an emitter layer of the first conductivity type selectively formed in the surface of the base layer, and a gate electrode buried from the surface of the emitter layer through into the second drift layer with a gate insulating film therebetween, wherein said first drift layer has a structure in which a first layer of the first conductivity type and a second layer of the second conductivity type are repeated in a horizontal direction.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: July 9, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinji Aono, Tadaharu Minato
  • Patent number: 8482031
    Abstract: This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain ?v for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT ?v<1??p where ?p is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola
  • Publication number: 20130161689
    Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.
    Type: Application
    Filed: November 9, 2012
    Publication date: June 27, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, L
  • Patent number: 8460976
    Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 11, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8460975
    Abstract: A reverse block-type insulated gate bipolar transistor (IGBT) manufacturing method that, when manufacturing a reverse block-type IGBT having a separation layer formed along tapered surfaces of a V-shaped groove formed using anisotropic etching, can secure a highly reliable reverse pressure resistance, and suppress a leakage current when reverse biasing. When irradiating with a flash lamp for flash lamp annealing after implantation of ions into a second conductivity type separation layer and second conductivity type collector layer to form the second conductivity type collector layer and second conductivity type separation layer, the strongest portion of radiation energy is focused on a depth position from the upper portion to the central portion of a tapered side edge surface.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: June 11, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Motoyoshi Kubouchi, Hideaki Teranishi, Hideo Shimizu
  • Patent number: 8455953
    Abstract: A sinker layer is in contact with a first conductivity-type well and a second conductivity-type drift layer, respectively, and is separated from a first conductivity-type collector layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: June 4, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Publication number: 20130134477
    Abstract: Back gate triggered silicon controlled rectifiers (SCR) and methods of manufacture are disclosed. The method includes forming a first diffusion type and a second diffusion type in a semiconductor layer of a silicon on insulator (SOI) substrate. The method further includes forming a back gate of a first diffusion type in a substrate under an insulator layer of the SOI substrate. The method further includes forming raised diffusion regions of a first dopant type and a second dopant type, adjacent to the second diffusion type and the first diffusion type, respectively. The back gate is formed to cover the second diffusion type, the first diffusion type and the second dopant type of the raised diffusion regions.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. GAUTHIER, JR., Junjun LI
  • Patent number: 8450777
    Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: May 28, 2013
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Jan Vobecky, Arnost Kopta
  • Patent number: 8421157
    Abstract: A horizontal semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of a second conductivity type on the semiconductor substrate. The device includes a collector layer of the first conductivity type within the semiconductor region, an endless base layer of the first conductivity type within the semiconductor region, and an endless first emitter layer of the second conductivity type in the endless base layer. The endless base layer is off the collector layer but surrounds the collector layer. A movement of carriers between the endless first emitter layer and the collector layer is controlled in a channel region formed in the endless base layer. An insulation film is disposed between the semiconductor substrate and the semiconductor region. A region of the first conductivity type is disposed in the semiconductor region to contact with a surface of the endless base layer nearest the semiconductor substrate.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunari Hatade
  • Patent number: 8415712
    Abstract: This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: April 9, 2013
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Vasantha Pathirana, Tanya Trajkovic, Nishad Udugampola