With Recessed Gate (epo) Patents (Class 257/E21.384)
  • Patent number: 10134837
    Abstract: A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Stephen Alan Fanelli, Richard Hammond
  • Patent number: 10038062
    Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: July 31, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Madhur Bobde
  • Patent number: 9679822
    Abstract: A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer is grown. The epitaxial layer covers the first trenches and the second trenches but not the third trenches. First and second recesses on a top surface of the epitaxial layer are formed. First and second openings aligned with the first and the second recesses and a third openings aligned with the third trenches are formed in a photoresist layer. A corresponding first offset between a top center and a bottom center of each first recess is measured. An offset value of the top center from the bottom center of said each first recess is determined. A corresponding second offset between a top center of each second recess and a center of corresponding second opening is determined. A corresponding third offset between a center of each third trench and a center of corresponding third opening is measured.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 13, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Boxiu Cai, Lingbing Chen, Yiming Gu
  • Patent number: 9646991
    Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NOR circuit. The NOR circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NOR circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NOR circuit.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 9, 2017
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Masamichi Asano
  • Patent number: 9577091
    Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 21, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chun Yeh, Wei-Tsung Chen, Cheng-Hang Hsu, Ted-Hong Shinn
  • Patent number: 9478649
    Abstract: A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer, N-drift layer and N-type CS layer within the N-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side. There are active cells and plugged cells on top of the device. The polysilicon cores of the trenches in the active cells are connected to the gate electrode, and the polysilicon cores of the trenches in the plugged cells are connected to the emitter electrode. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and plugged cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in plugged cells are divided by N-drift layer, forming discontinuous P-type regions along the direction of trenches.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: October 25, 2016
    Assignee: Changzhou ZhongMin Semi-Tech Co., Ltd
    Inventor: Yuzhu Li
  • Patent number: 9443734
    Abstract: A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seok Lee, Jung-Hwan Park, Hyo-Jin Park, Kyu-Hyun Lee
  • Patent number: 9431484
    Abstract: A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 30, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Rainald Sander, Markus Winkler, Michael Asam, Matthias Stecher
  • Patent number: 9293549
    Abstract: A silicon carbide layer includes a first region having a first conductivity type, a second region provided on the first region and having a second conductivity type, and a third region provided on the second region and having the first conductivity type. A trench having an inner surface is formed in the silicon carbide layer. The trench penetrates the second and third regions. The inner surface of the trench has a first side wall and a second side wall located deeper than the first side wall and having a portion made of the second region. Inclination of the first side wall is smaller than inclination of the second side wall.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: March 22, 2016
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Nara Institute of Science and Technology
    Inventors: Takeyoshi Masuda, Tomoaki Hatayama
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 8994066
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 31, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8969956
    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Balaji Padmanabhan
  • Patent number: 8962401
    Abstract: A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Werner Juengling, Howard C. Kirsch
  • Patent number: 8946002
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Patent number: 8928072
    Abstract: Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8889493
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: November 18, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8860025
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz Hirler, Hans-Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8841175
    Abstract: A method for manufacturing a vertical trench IGBT includes: forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type; forming a trench passing through the body layer; forming a trench gate in the trench via a gate insulating film; forming a polysilicon film containing an impurity of a first conductivity type on the body layer; diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 23, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hidenori Fujii
  • Patent number: 8809941
    Abstract: A semiconductor device includes a semiconductor substrate having an active region defined by a device isolation structure. A recessed channel is formed on the semiconductor substrate under the active region. A recessed junction region is formed between the recessed channel and the device isolation structure adjacent to the recessed channel.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: August 19, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong Hwa Shim
  • Patent number: 8796762
    Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 5, 2014
    Assignee: Infineon Technologies AG
    Inventors: Richard Lindsay, Matthias Hierlemann
  • Patent number: 8742452
    Abstract: Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: June 3, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Soo Kim, Bum Seok Suh, In Hyuk Song, Jae Hoon Park, Dong Soo Seo
  • Patent number: 8697560
    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Prasad Venkatraman, Balaji Padmanabhan
  • Patent number: 8642401
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: February 4, 2014
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Publication number: 20140027813
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: Marian Kuruc, Iuraj Vavro
  • Publication number: 20130234200
    Abstract: A method for manufacturing a vertical trench IGBT includes: forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type; forming a trench passing through the body layer; forming a trench gate in the trench via a gate insulating film; forming a polysilicon film containing an impurity of a first conductivity type on the body layer; diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 12, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hidenori FUJII
  • Patent number: 8530966
    Abstract: A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: September 10, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Atsushi Narazaki, Hisaaki Yoshida, Kazuaki Higashi
  • Publication number: 20130181253
    Abstract: The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu, Chien-Hao Huang
  • Patent number: 8476137
    Abstract: Disclosed herein are methods for better variable height control of FinFET patterned fins. In one example, the method includes forming a layer on a substrate, patterning that layer to create trenches, and forming a common stack material in the trenches. Next, a pFET masking material is formed over a portion of the structure, and an nFET channel material is formed in the unmasked trenches. The pFET masking material is removed and an nFET masking material is formed over the portion of the structure that includes the nFET channel material, and a pFET channel material is formed in the unmasked trenches. Next, the unmasked patterned material is made flush with the pFET channel material, thereby creating a difference in height with the masked pattern material. Finally, the nFET masking material is removed and the patterned layer is recessed to expose pFET and nFET channel material fin structures of differing heights.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: July 2, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas LiCausi, Jeremy Wahl
  • Publication number: 20130105856
    Abstract: A semiconductor device includes a semiconductor substrate which functions as an n? drift layer, a trench IGBT formed in the front surface, an interlayer insulator film, and a metal electrode layer on the interlayer insulator film. There is a contact hole in the interlayer insulating film which has a first opening formed on the metal electrode layer side and a second opening on the semiconductor substrate side. Width w1 of the first opening on the metal electrode layer side is wider than width w2 of first opening on the semiconductor substrate side, in a direction perpendicular to the extending direction of the trench in the planar pattern of trenches. The metal electrode layer is connected to a p-type channel region and an n+ source region via the contact hole. The method of manufacturing improves the reliability of the device.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 2, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: FUJI ELECTRIC CO., LTD.
  • Patent number: 8415671
    Abstract: Semiconductor switching devices include a first wide band-gap semiconductor layer having a first conductivity type. First and second wide band-gap well regions that have a second conductivity type that is opposite the first conductivity type are provided on the first wide band-gap semiconductor layer. A non-wide band-gap semiconductor layer having the second conductivity type is provided on the first wide band-gap semiconductor layer. First and second wide band-gap source/drain regions that have the first conductivity type are provided on the first wide band-gap well region. A gate insulation layer is provided on the non-wide band-gap semiconductor layer, and a gate electrode is provided on the gate insulation layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: April 9, 2013
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Publication number: 20130056731
    Abstract: A semiconductor device includes a semiconductor diode. The semiconductor diode includes a drift region and a first semiconductor region of a first conductivity type formed in or on the drift region. The first semiconductor region is electrically coupled to a first terminal via a first surface of a semiconductor body. The semiconductor diode includes a channel region of a second conductivity type electrically coupled to the first terminal, wherein a bottom of the channel region adjoins the first semiconductor region. A first side of the channel region adjoins the first semiconductor region.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Anton Mauder, Franz Hirler, Hans Peter Felsl, Hans-Joachim Schulze
  • Patent number: 8389364
    Abstract: A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 5, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Don Lee
  • Patent number: 8377775
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 19, 2013
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 8373209
    Abstract: A semiconductor device includes: a substrate; and depletion and enhancement mode JFETs. The depletion mode JFET includes: a concavity on the substrate; a channel layer in the concavity; a first gate region on the channel layer; first source and drain regions on respective sides of the first gate region in the channel layer; first gate, source and drain electrodes. The enhancement mode JFET includes: a convexity on the substrate; the channel layer on the convexity; a second gate region on the channel layer; second source and drain regions on respective sides of the second gate region in the channel layer; second gate, source and drain electrodes. A thickness of the channel layer in the concavity is larger than a thickness of the channel layer on the convexity.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 12, 2013
    Assignee: DENSO CORPORATION
    Inventors: Rajesh Kumar Malhan, Naohiro Sugiyama
  • Publication number: 20120326207
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 27, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8338887
    Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: December 25, 2012
    Assignee: Infineon Technologies AG
    Inventors: Richard Lindsay, Matthias Hierlemann
  • Patent number: 8304829
    Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: November 6, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Ashok Challa
  • Publication number: 20120261714
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 18, 2012
    Applicant: DENSO CORPORATION
    Inventors: Eiichi TAKETANI, Seigo Oosawa
  • Publication number: 20120256230
    Abstract: A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8258032
    Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: September 4, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Koh Yoshikawa
  • Publication number: 20120214281
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer containing silicon nitride on a semiconductor layer. The method includes forming a side wall film on a side wall of the mask layer. The method includes etching the semiconductor layer using the mask layer and the side wall film to form a gate trench. The method includes forming a gate electrode in the gate trench. The method includes removing the side wall film and forming a base region and a source region in the semiconductor layer using the mask layer. The method includes forming an interlayer film covering the semiconductor layer, the gate electrode and the mask layer, and containing silicon oxide. The method includes forming a contact trench, by using the interlayer film as a mask, in a portion of the semiconductor layer under a portion where the mask layer is removed.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki TOMITA, Hideki OKUMURA
  • Patent number: 8247298
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising: forming a first layer on a sidewall of a trench formed on a main surface of a semiconductor substrate, filling up the trench with a protective film, etching back the protective film by a dry etching method so that a height of a surface of the protective film is lower than an opening of the trench and removing the first layer exposed by the etching-back.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: August 21, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Keisuke Ohtsuka
  • Patent number: 8242556
    Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: August 14, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Koh Yoshikawa, Hiroki Wakimoto, Masahito Otsuki
  • Publication number: 20120146090
    Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Anup Bhalla
  • Patent number: 8188531
    Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Hoon Kim
  • Patent number: 8178947
    Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: May 15, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Yoshifumi Tomomatsu
  • Publication number: 20120104555
    Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.
    Type: Application
    Filed: October 31, 2010
    Publication date: May 3, 2012
    Inventors: Madhur Bobde, Anup Bhalla
  • Patent number: 8168498
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: May 1, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 8164162
    Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: April 24, 2012
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: RE44236
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 21, 2013
    Assignees: DENSO CORPORATION, Sumco Corporation
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Tomoatsu Makino, Syouji Nogami, Tomonori Yamaoka