Vertical Power Dmos Transistor (epo) Patents (Class 257/E21.418)
  • Patent number: 9997642
    Abstract: A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 12, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Wen-Tai Wang
  • Patent number: 9780086
    Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 3, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig Guitart, Samir Mouhoubi, Filip Bauwens
  • Patent number: 9761550
    Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: September 12, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Robert Montgomery, Hugo Burke, Phillip Parsonage, Susan Johns, David Paul Jones
  • Patent number: 9653595
    Abstract: An n? drift layer is a parallel pn layer having an n-type region and a p-type region are alternately arranged in the direction parallel to the main surface so as to come into contact with each other, and have a width in a direction parallel to the main surface of the substrate which is less than a length in a direction perpendicular to the main surface of the substrate. A second-main-surface-side lower end portion of the p-type region has a structure in which a high-concentration lower end portion and a low-concentration lower end portion of a p-type low-concentration region are repeated at a predetermined pitch in the direction parallel to the main surface of the substrate. It is possible to provide a super junction MOS semiconductor device which can improve a trade-off relationship between turn-off loss and turn-off dv/dt and improve avalanche resistance.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 16, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasushi Niimura, Toshiaki Sakata
  • Patent number: 9640612
    Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 2, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Shoji Higashida
  • Patent number: 9627470
    Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1<Pn (n?2).
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: April 18, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: In Hyuk Song, Jae Hoon Park, Kee Ju Um, Dong Soo Seo
  • Patent number: 9437494
    Abstract: A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Alexander Kalnitsky, Kong-Beng Thei, Chien-Chih Chou, Chen-Liang Chu, Hsiao-Chin Tuan
  • Patent number: 9418985
    Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Yang Du
  • Patent number: 9024381
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, and a super junction area that is disposed above the substrate. The super junction area may include pillars of different doping types that are alternately disposed. One of the pillars of the super junction area may have a doping concentration that gradually decreases and then increases from bottom to top in a vertical direction of the semiconductor device.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 5, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Moon-soo Cho, Kwang-yeon Jun, Hyuk Woo, Chang-sik Lim
  • Patent number: 9006825
    Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 14, 2015
    Assignee: MediaTek Inc.
    Inventors: Puo-Yu Chiang, Yan-Liang Ji
  • Patent number: 8987810
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 8928079
    Abstract: A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 6, 2015
    Assignee: Alpha and Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 8912057
    Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: December 16, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8901717
    Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Gerald Deboy
  • Patent number: 8901641
    Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Tsung-Hsiung Lee
  • Patent number: 8872278
    Abstract: In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: October 28, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jifa Hao, Gary Dolny, Mark Rioux
  • Patent number: 8866222
    Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Stefan Gamerith, Franz Hirler
  • Patent number: 8853022
    Abstract: A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Guowei Zhang
  • Patent number: 8853784
    Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
  • Patent number: 8853783
    Abstract: A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Ming Li, Jeoung Mo Koo, Purakh Raj Verma
  • Patent number: 8853779
    Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alfio Guarnera, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 8853772
    Abstract: High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 7, 2014
    Assignee: Alpha & Omega Semiconductor Ltd
    Inventor: François Hébert
  • Patent number: 8847310
    Abstract: A MOSFET includes an active region formed on an SOI substrate. A buried well is formed in the active region. A drain region having the first conductivity type is formed in the active region and spaced laterally from a source region and the buried well. A body region is formed in the active region between the source and drain regions on the buried well, and a drift region is formed in the active region between the drain and body regions on at least a portion of the buried well. A shielding structure is formed proximate the upper surface of the active region, overlapping a gate. During conduction, the buried well forms a PN junction with the drift region which, in conjunction with the shielding structure, depletes the drift region. The MOSFET is configured to sustain a linear mode of operation of an inversion channel formed under the gate.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 30, 2014
    Assignee: Azure Silicon LLC
    Inventor: Jacek Korec
  • Patent number: 8847318
    Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
  • Patent number: 8836017
    Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8791525
    Abstract: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: July 29, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Montgomery, Hugo Burke, Philip Parsonage, Susan Johns, David Paul Jones
  • Patent number: 8759202
    Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Gerald Deboy
  • Patent number: 8716085
    Abstract: A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: May 6, 2014
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Jae-gil Lee, Chang-wook Kim, Ho-cheol Jang, Chong-man Yun
  • Patent number: 8704291
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 22, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 8685810
    Abstract: A method for a power layout of an integrated circuit. The method includes providing at least one unit power cell. The unit power cell includes at least one power grid cell. Each power grid cell has at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The first power layer has conductive lines in at least two different directions and the at least one second power layer has conductive lines in at least two different directions. The method further includes filling a target area in the power layout by at least one unit power cell to implement at least one power cell.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Chieh Yang
  • Patent number: 8680607
    Abstract: Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: March 25, 2014
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Jun Zeng, Mohamed N. Darwish
  • Patent number: 8664714
    Abstract: A power MOSFET includes an epitaxy substrate, conductive trenches, well regions and a dielectric layer. The power MOSFET further has at least one termination structure including at lest one of the conductive trenches, some of the well regions within a termination area and mutually insulated by the conductive trench, a field plate, a contact plug and a heavily-doped region. The field plate including a plate metal and the dielectric layer is on the well regions and the conductive trench within the termination area. The contact plug penetrates through the dielectric layer and connects the plate metal and one of the well regions, so the plate metal has equal potential with the connected well region through the contact plug. The well regions and the conductive trench are electrically coupled to the plate metal by the dielectric layer. The heavily-doped region is between the contact plug and the connected well region.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 4, 2014
    Assignee: Excelliance MOS Corporation
    Inventor: Chu-Kuang Liu
  • Patent number: 8643136
    Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 4, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Kuo-Hsuan Lo
  • Patent number: 8643090
    Abstract: In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
  • Patent number: 8604541
    Abstract: This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: December 10, 2013
    Assignee: Wuxi Versine Semiconductor Corp. Ltd.
    Inventors: Qin Huang, Yuming Bai, Yang Gao
  • Patent number: 8564060
    Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: October 22, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Haruka Shimizu, Natsuki Yokoyama
  • Patent number: 8530300
    Abstract: Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Armin Willmeroth, Anton Mauder, Franz Hirler
  • Patent number: 8513734
    Abstract: A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 20, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Jiang-Kai Zuo
  • Patent number: 8513730
    Abstract: A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: August 20, 2013
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Helmut Strack, Armin Willmeroth, Hans-Joachim Schulze
  • Publication number: 20130210205
    Abstract: The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.
    Type: Application
    Filed: July 19, 2012
    Publication date: August 15, 2013
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8507986
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Peter Micah Sandvik, Zachary Matthew Stum, Peter Almren Losee, James Jay McMahon
  • Publication number: 20130193508
    Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: TSUNG-HSIUNG LEE
  • Patent number: 8492226
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length LD of the device. A surface doped region is formed adjacent to the gate.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 23, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shajan Mathew, Purakh Raj Verma
  • Patent number: 8492254
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: July 23, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tomonori Mizushima
  • Patent number: 8486784
    Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Jung Kim
  • Publication number: 20130175608
    Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 11, 2013
    Inventors: Tsung-Hsiung LEE, Shang-Hui Tu
  • Publication number: 20130175607
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 11, 2013
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8466510
    Abstract: A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: June 18, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Hamza Yilmaz
  • Patent number: 8461648
    Abstract: A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: June 11, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Anton Mauder, Armin Willmeroth, Hans-Joachim Schulze, Stefan Sedlmaier, Markus Zundel, Franz Hirler, Arunjai Mittal
  • Patent number: RE45449
    Abstract: A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Armin Willmeroth