Abstract: A semiconductor pillar which has a first conductive type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductive type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductive type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection.

Abstract: A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

Abstract: According to one embodiment, a semiconductor device includes a drain layer, a drift, a base, a source region, a plurality of gates provided on the drift region, the base, and the source region, and arranged in a manner spaced apart from each other, a first interlayer insulating film arranged between the plurality of gates on the source region, a gate interconnection film provided on the first interlayer insulating film and the gate, a second interlayer insulating film provided on the gate interconnection film, an inetconnection film provided on the second interlayer insulating film and connected in common to the source region, the interconnection film filling the contact hole provided between each of the gates in the second interlayer insulating film, the gate interconnection film and the first interlayer insulating film and an insulating film arranged between the gate interconnection film and the interconnection film in the contact hole.

Abstract: Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.

Abstract: A 3-D non-volatile memory device includes a pipe gate having a first trench formed therein, word lines stacked in multiple layers over the pipe gate, second trenches coupled to the first trench and formed to penetrate the word lines, a first channel layer formed within the first trench, and second channel layers formed within the second trenches, respectively, and coupled to the first channel layer, wherein the width or depth of the first trench is smaller than the diameter of each of the second trenches.

Abstract: A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions.

Abstract: According to one embodiment, a semiconductor device includes a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a source region of the first conductivity type, a first and a second main electrode, trench gates, a first and a second contact region. The third semiconductor layer is provided on the second semiconductor layer provided on the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is electrically connected to the source region provided on the third semiconductor layer. The trench gates are provided from the third semiconductor layer to the second semiconductor layer. The first and second contact regions electrically connect the second main electrode and the third semiconductor layer. An opening area of the second contact hole is smaller than that of the first contact hole.

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Abstract: In according with the present invention, a semiconductor device is formed as follows. A contact insulation layer is deposited on the top surface of said silicon layer. A contact mask is applied and following with a dry oxide etching to remove the contact insulation layer from contact open areas. The silicon layer is tilt-angle implanted with a source dopant through the contact open areas and the source dopant is diffused to form source regions, thereby a source mask is saved. A dry silicon etch is carried out to form trenched source-body contacts in the contact open areas, penetrating through the source regions and extending into the body regions.

Abstract: Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

Abstract: A method for producing a semiconductor device with a dielectric layer includes: providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall; forming a first dielectric layer on the sidewall in a lower portion of the first trench; forming a first plug in the lower portion of the first trench so as to cover the first dielectric layer, the first plug leaving an upper portion of the sidewall uncovered; forming a sacrificial layer on the sidewall in the upper portion of the first trench; forming a second plug in the upper portion of the first trench; removing the sacrificial layer, so as to form a second trench having sidewalls and a bottom; and forming a second dielectric layer in the second trench and extending to the first dielectric layer.

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract: A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.

Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract: A semiconductor device including a plurality of units having identical structures, each unit includes: a drain electrode; a drift layer that includes a low concentration layer on the drain electrode and a reference concentration layer on the low concentration layer, a gate electrode on the reference concentration layer; a pair of source regions that are provided on an upper surface of the reference concentration layer and in the vicinity of both ends of the gate electrode; a pair of base regions that surround outer surfaces of the source regions; a source electrode electrically connected to the source regions and the base regions; and a pair of depletion-layer extension regions that are respectively provided under the base regions in the reference concentration region. Boundaries between the depletion-layer extension regions and the low concentration layer are positioned lower than a boundary between the reference concentration layer and the low concentration layer.

Abstract: A method of producing a semiconductor device including a MOS transistor, includes the steps of forming, on a top surface of at least one of semiconductor pillars, an epitaxial layer having a top surface larger in area than the top surface of the at least one of the semiconductor pillars and forming a source region or a drain region so as to be at least partially in the epitaxial layer.

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type.

Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Abstract: A method of forming a fine pattern and a method of manufacturing a semiconductor device. The method of forming a fine pattern includes: forming a hard mask layer on a to-be-etched layer; forming on the hard mask layer a first mask pattern including a plurality of elongated openings that are arranged at predetermined intervals in a first direction and a second direction different from the first direction and are offset from each other in adjacent columns in the second direction; forming on the hard mask layer a second mask pattern including at least two linear openings that each pass through the elongated openings in the adjacent columns and extend in the first direction; forming a hard mask pattern by etching the hard mask layer by using the second mask pattern as an etch mask; and etching the to-be-etched layer by using the hard mask pattern.

Abstract: Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

Abstract: A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.

Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

Abstract: A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.

Abstract: The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29).

Abstract: A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage.

Abstract: A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.

Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities.

Abstract: A first diffused region is formed in a surface of a semiconductor substrate located under a gate electrode. A second diffused region is formed in a surface of the semiconductor substrate adjoining the first diffused region on a first side thereof. A third diffused region is formed in a surface of the semiconductor substrate adjoining the first diffused region on a second side thereof. The first side and the second side are opposite to one another. A first wire is disposed above an overlapping region where the first and third diffused regions overlap. The first wire is supplied with at least a certain voltage for preventing formation of a depletion region in the third diffused region when transfer transistor transfers the voltage used for writing.

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate; an arsenic diffusion layer formed in the semiconductor substrate and containing arsenic; and a metal film formed on the arsenic diffusion layer. The metal film includes at least one metal selected from the group consisting of tungsten, titanium, ruthenium, hafnium, and tantalum, and arsenic.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.

Abstract: A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.

Abstract: The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.

Abstract: A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench.

Abstract: The present invention makes it possible to inhibit an SOA (Safe Operating Area) in a vertical-type bipolar transistor from narrowing. A p-type base layer 150 includes a first peak, a second peak, and a third peak in an impurity profile in the thickness direction. The first peak is located on the topmost surface side of a semiconductor substrate 100. The second peak is located closer to the bottom face side of the semiconductor substrate 100 than the first peak and higher than the first peak. The third peak is located between the first peak and the second peak.

Abstract: A semiconductor component is produced by forming a trench in a semiconductor region. The trench has an upper trench region and a lower trench region. The upper trench region is wider than the lower trench region such that a step is formed in the semiconductor region. A dopant is introduced into the step to form a locally delimited dopant region in the semiconductor region.

Abstract: A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.