Abstract: The present disclosure discloses a microfluidic device, a driving method and a microfluidic detection system. The microfluidic device includes: a substrate; two first optical waveguides disposed opposite each other on the substrate with an accommodating chamber defined between the two first optical waveguides; and a plurality of optical detection structures in the accommodating chamber. The first optical waveguide has a refractive index greater than a refractive index of a medium surrounding the first optical waveguide, thereby enabling light rays incident into an end of the first optical waveguide to propagate towards another end of the first optical waveguide in a total reflection mode.

Abstract: A device may capture, using a camera associated with a microscope, a first image of interstitial material associated with a first set of optical fibers in a field of view of the camera. The device may perform a comparison of the first image of interstitial material and a second image of interstitial material associated with a second set of optical fibers. The device may determine that the first set of optical fibers does not include an expected set of optical fibers based on a result of performing the comparison. The device may determine an amount by which to adjust the field of view of the camera based on the result of performing the comparison. The device may perform one or more actions.

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

Abstract: A structure includes a semiconductor substrate, a buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer.

Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.

Abstract: An apparatus includes a sample carrier having wells. Each of the wells has sides and a floor forming an interior. A surface enhanced Raman spectroscopy (SERS) structure is within the interior of each of the wells. A pneumatic port is connected to the interior of each of the wells. A pneumatic passage is connected to the pneumatic ports.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

Abstract: A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate.

Abstract: A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width.

Abstract: This invention provides biochip cartridges and instrument devices for the detection and/or analysis of target analytes from patient samples.

Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.

Abstract: A structure and method for forming a substrate, a buffer layer disposed on the substrate, an oxide layer disposed on the buffer layer, and a fin comprising a semiconductor material disposed on the oxide layer.

Abstract: An analytical assembly within a unified device structure for integration into an analytical system. The analytical assembly is scalable and includes a plurality of analytical devices, each of which includes a reaction cell, an optical sensor, and at least one optical element positioned in optical communication with both the reaction cell and the sensor and which delivers optical signals from the cell to the sensor. Additional elements are optionally integrated into the analytical assembly. Methods for forming and operating the analytical system are also disclosed.

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

Abstract: The invention generally relates to droplet based digital PCR and methods for analyzing a target nucleic acid using the same. In certain embodiments, methods of the invention involve forming sample droplets containing, on average, a single target nucleic acid, amplifying the target in the droplets, excluding droplets containing amplicon from the target and amplicon from a variant of the target, and analyzing target amplicons.

Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.

Abstract: An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion.

Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.

Abstract: A sensor device has an arrangement of plural sensors for sensing an analyte which is in at least one of liquid phase or a suspension or a gel. Each sensor includes a nano-electrode and is configured to sense the presence of a particle localized to or bound to the nano-electrode. The sensor is configured to discriminate in real-time the binding of particles to respective nano-electrodes.

Abstract: A semiconductor structure includes an active layer located on a substrate and a first and a second gate structure located on the active layer. A first raised epitaxial region is located on the active layer between the first and the second gate. The first raised epitaxial region has a first facet shaped edge and a first vertical shape edge, such that the first facet shaped edge is located adjacent the first gate structure. A second raised epitaxial region is also located on the active layer between the first and the second gate structure. The second raised epitaxial region has a second facet shaped edge and a second vertical shape edge, such that the second facet shaped edge is located adjacent the second gate structure. A trench region is located between the first and the second vertical shaped edge for electrically isolating the first and the second raised epitaxial region.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

Abstract: A technique relates to a transistor. Dummy gates are formed on top of an isolation layer and over fins. Pillars are along sides of fins such that trenches separate the pillars from the sides of the fins. The pillars include a first intermediate layer formed on an isolation layer and a second intermediate layer formed on the first intermediate layer. An epitaxial layer is deposited in the trenches such that the epitaxial layer is laterally confined by the pillars. The top of the epitaxial layer forms a triangular shape that extends higher than the pillars. The pillars are removed such that straight sidewalls of the epitaxial layer are exposed. Dummy gates are replaced with replacement gates. A metal silicide contact that wraps around a source part and a drain part of the epitaxial layer is formed, by forming a conductive layer on top of the structure.

Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.

Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.

Abstract: Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance.

Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Abstract: Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.

Abstract: Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.

Abstract: A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process.

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

Abstract: The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.

Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000° C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 ? in a p-metal oxide semiconductor (pMOS) device.

Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

Abstract: Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.