Recessing Gate By Adding Semiconductor Material At Source (s) Or Drain (d) Location, E.g., Transist Or With Elevated Single Crystal S And D (epo) Patents (Class 257/E21.43)
Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.
Type:
Grant
Filed:
March 16, 2005
Date of Patent:
May 29, 2007
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Thorsten Kammler, Scott Luning, Linda Black
Abstract: By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.
Type:
Grant
Filed:
October 24, 2004
Date of Patent:
November 21, 2006
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Ralf van Bentum, Scott Luning, Andy Wei
Abstract: Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
Type:
Grant
Filed:
April 12, 2005
Date of Patent:
October 17, 2006
Assignee:
Amberwave Systems Corporation
Inventors:
Thomas A. Langdo, Anthony J. Lochtefeld
Abstract: SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.