Abstract: Disclosed is a device having a transistor that includes a source, a drain, a channel region extending between the source and the drain, a gate disposed near the channel region, and a conductive member disposed opposite of the channel region from the gate. The conductive member may not overlap the source, the drain, or both the source and the drain.

Abstract: Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.

Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.

Abstract: An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H2. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H2. A glue layer may be provided between the gettering layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.

Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.

Abstract: Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMOSFET P2 whose gate, drain and back gate are connected to back gate of P1. Source of N2 is connected to source of N1. Source of P2 is connected to source of P1. N2 is always connected between the grounded source of N1 and the back gate of N1, while P2 is connected between source of P1 connected to a power supply and the back gate of P1. Each of N2 and P2 functions as a voltage limiting element (a limiter circuit).

Abstract: A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

Abstract: A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.

Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

Abstract: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.

Abstract: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

Abstract: A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

Abstract: A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses.

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.

Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

Abstract: Devices and methods of fabricating a conductive pattern of such devices comprise a non-single crystalline semiconductor pattern formed on a single crystalline semiconductor substrate, an insulating spacer formed on a sidewall of the non-single crystalline semiconductor pattern, the non-single crystalline semiconductor pattern selectively recessed using a cyclic selective epitaxial growth (SEG) process, and a silicide layer formed on the recessed non-single crystalline semiconductor pattern.

Abstract: A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.

Abstract: A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.

Abstract: A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

Abstract: A method for forming a semiconductor device includes providing a substrate having at least a gate positioned thereon, forming at least a recess in the substrate adjacent to the gate, performing a first selective epitaxial growth (SEG) process to form a first epitaxial layer in the recess, performing an etching process to remove a portion of the first epitaxial layer to expose the substrate, and performing a second SEG process to form a second epitaxial layer on the first epitaxial layer.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.

Abstract: A method to form a strain-inducing three-component epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch step sequence, followed by an amorphizing dopant impurity-implant and, finally, a kinetically-driven crystallization process. In one embodiment, the charge-neutral lattice-substitution atoms are smaller and present in greater concentration than the charge-carrier dopant impurity atoms.

Abstract: A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.

Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

Abstract: The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius and a pressure greater than about 1 Torr so as to form an epitaxial film on at least a portion of the substrate. Then, the substrate is exposed to an etchant so as to etch the epitaxial film and any other films formed during the deposition. The deposition and etching may be repeated until a film of a desired thickness is achieved. Numerous other aspects are disclosed.

Abstract: Methods of manufacturing a field effect transistor include forming a gate pattern on a substrate. A gate spacer is formed on a sidewall of the gate pattern. A first layer is formed from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth (SEG) process at a first temperature. A second layer is formed from a surface of the first layer and contacting the gate spacer using a second SEG process at a second temperature. The second temperature is lower than the first temperature. The first and second layers define elevated source/drain regions.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: A method for epitaxially forming a silicon-containing material on a substrate surface utilizes a halogen containing gas as both an etching gas as well as a carrier gas through adjustments of the process chamber temperature and pressure. It is beneficial to utilize HCl as the halogen containing gas because converting HCl from a carrier gas to an etching gas can easily be performed by adjusting the chamber pressure.

Abstract: A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective gate dielectric thicknesses for the different gate dielectrics separating the channels, and different respective silicon channel thicknesses for the different channels.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

Abstract: A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.

Abstract: To provide a semiconductor device having lower junction capacitance, which can be manufactured with lower power consumption through a simpler process as compared with conventional, a semiconductor device includes a base substrate; a semiconductor film formed over the base substrate; a gate insulating film formed over the semiconductor film; and an electrode formed over the gate insulating film. The semiconductor film has a channel formation region which overlaps with the electrode with the gate insulating film interposed therebetween, a cavity is formed between a recess included in the semiconductor film and the base substrate, and the channel formation region is in contact with the cavity on the recess.

Abstract: In a method of fabricating a transistor including a buried insulating layer and transistor fabricated using the same, the method includes sequentially forming a sacrificial layer and a top semiconductor layer on a single crystalline semiconductor substrate. A gate pattern is formed on the top semiconductor layer. A sacrificial spacer is formed to cover sidewalls of the gate pattern. An elevated semiconductor layer is grown on a portion of the top semiconductor layer adjacent to the sacrificial spacer. The sacrificial spacer is removed. A portion of the top semiconductor layer from which the sacrificial spacer is removed is etched until the sacrificial layer is exposed, thereby forming a recess, which separates the top semiconductor layer into a first top semiconductor layer pattern and a second top semiconductor layer pattern, which remain under the gate pattern and the elevated semiconductor layer, respectively. The sacrificial layer is selectively removed.

Abstract: A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.

Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.

Abstract: The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract: In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion and a second portion of active regions adjacent the gate, and forming a first recess in a portion of the source region and a second recess in a portion of the drain region. The method also includes activating the dopants in the source region and the drain region by heating the active regions and depositing a semiconductor material in the first recess and the second recess after activating the dopants in the source region and the drain region.

Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A silicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device includes a transistor configured to control the emission of electrons from an emitter.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Abstract: A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region.