Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.

Abstract: Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract: In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability.

Abstract: Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.

Abstract: Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.

Abstract: The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

Abstract: Methods are provided for the fabrication of multiple finger transistors. A method comprises forming a layer of gate-forming material overlying a semiconductor substrate and forming a layer of dummy gate material overlying the layer of gate-forming material. The layer of dummy gate material is etched to form a dummy gate and sidewall spacers are formed about sidewalls of the dummy gate. The dummy gate is removed and the layer of gate-forming material is etched using the sidewall spacers as a mask to form at least two gate electrodes.

Abstract: A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.

Abstract: By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form of carbon, nitrogen and the like.

Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Abstract: Provided is a semiconductor device manufacturing method by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer. A semiconductor device is also provided. A dummy gate electrode 3 is formed on a Si substrate 1. Then, a recess region 7 is formed by recess etching by using the dummy gate electrode 3 as a mask. Next, on the surface of the recess region 7, a mixed crystal layer 8 composed of a SiGe layer is epitaxially grown. Subsequently, an interlayer insulating film 12 is formed on the mixed crystal layer 8 to cover the dummy gate electrode 3, and the interlayer insulating film 12 is removed until the surface of the dummy gate electrode 3 is exposed. A recess 13 is formed on the interlayer insulating film 12 to expose the Si substrate 1 by removing the dummy gate electrode 3. Then, a gate electrode 15 is formed in the recess 13 by having a gate insulating film 14 in between.

Abstract: A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than about 30 ? underlying the sidewall spacer, and a silicon alloy region having at least a portion in the substrate and adjacent the recessed region. The silicon alloy region has a thickness of substantially greater than about 30 nm. A shallow recess region is achieved by protecting the substrate when a hard mask on the gate structure is removed. The MOS device is preferably a pMOS device.

Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

Abstract: A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

Abstract: Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece is masked, and the recesses in the second region of the workpiece are filled with a first semiconductive material. The second region of the workpiece is masked, and the recesses in the first region of the workpiece are filled with a second semiconductive material.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

Abstract: A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.

Abstract: Semiconductor device structures, and methods for making such structures, are described that provide for fully-doped transistor source/drain regions while reducing or even avoiding boron penetration into the transistor channel, thereby improving the performance of the transistor. In addition, such a transistor may benefit from an SiGe layer that applies compressive stress to the transistor channel, thereby further improving the performance of the transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor adjacent the gate stack and having at least a portion in the semiconductor substrate, wherein the stressor comprises an element for adjusting a lattice constant of the stressor. The stressor includes a lower portion and a higher portion on the lower portion, wherein the element in the lower portion has a first atomic percentage, and the element in the higher portion has a second atomic percentage substantially greater than the first atomic percentage.

Abstract: A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper portions higher than the surface of the substrate and having silicide layers formed on regions of exposed from the substrate. The lower portion of the SiGe film that faces the electrode is formed to extend in a direction perpendicular to the surface of the substrate and the upper portion is inclined and separated farther apart from the gate electrode as the upper portion is separated away from the surface of the substrate. The surface of the silicide layer of the SiGe film that faces the gate electrode is higher than the channel region.

Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

Abstract: A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

Abstract: A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract: By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device performance of advanced field effect transistors may be even further enhanced compared to conventional approaches using a strained semiconductor alloy in the drain and source regions.

Abstract: There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.

Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.

Abstract: Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium.

Abstract: The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with a cover film. After removal of the cover film from at least one of sidewall surface of the gate electrode and a part of the top surface of the substrate adjacent to the sidewall surface, a semiconductor layer is epitaxially grown on a top surface of an exposed substrate to electrically connect the substrate and the at least one sidewall surface of the gate electrode. Then, a source/drain region is formed in a top surface part of the substrate or the semiconductor layer using the gate electrode as a mask.

Abstract: Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium.

Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.

Abstract: A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device regions (224).

Abstract: An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region.

Abstract: A method for manufacturing a substrate of a liquid crystal display device is disclosed. The method includes forming a conductive line structure with low resistance to improve the difficulty of the resistance matching. The method can effectively reduce the resistance of the conductive line of the LCD panel to increase the transmission rate of the driving signal. Hence, the increasing yield of products can reduce the cost of manufacturing, and can meet the requirement of the large-size and high-definition thin film transistor liquid crystal display device.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.

Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor.

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract: A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.

Abstract: A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor.

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Abstract: A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Abstract: MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.

Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

Abstract: A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.