Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.

Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Abstract: In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.

Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.

Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.

Abstract: A method for forming a T-gate of a metamorphic high electron mobility transistor is provided. The method includes sequentially laminating a plurality of resist films on a substrate; forming a T-shaped pattern in the laminated resist films using electron beam lithography; forming a gate metal layer on the substrate where the T-shaped pattern has been formed; attaching an adhesion member to the gate metal layer formed on a top surface of the laminated resist films and detaching the adhesion member to thereby remove the gate metal layer; and removing the laminated resist films.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) includes a semi-insulating substrate having a surface, an implanted n-type channel region in the substrate, and implanted source and drain regions extending from the surface of the substrate into the implanted channel region. A gate contact is between the source and the drain regions, and an implanted p-type region is beneath the source region. The implanted p-type region has an end that extends towards the drain region, is spaced apart vertically from the implanted channel layer, and is electrically coupled to the source region. Methods of forming transistors including implanted channels and implanted p-type regions beneath the source region are also disclosed.

Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.

Abstract: A field effect transistor with a fin structure having a first and a second source/drain region; a body region formed within the fin structure and between the first and the second source/drain region; a metallically conductive region formed within a part of the first source/drain region, the metallically conductive region being adjacent to the body region or to a lightly doped region disposed between the body region and the first source/drain region; and a current ballasting region formed within a part of the second source/drain region.

Abstract: A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to contact with the drain region and to extend in one direction; and gates respectively formed on both side walls of the stacked drain region, channel region and source region.

Abstract: An electronic device includes a substrate, an insulating layer arranged on the substrate, the insulating layer having an opening in an area of the surface of the substrate, an active layer arranged within the opening on the surface of the substrate, the active layer including a guard ring in those areas of the surface and of the active layer which are adjacent to the insulating layer, and a contacting layer arranged on an area of the active layer, the contact layer being adjacent to an area of the guard ring. The device may be produced by a process of three-fold self-alignment, to be precise utilizing a spacer process by means of which a diffusion source having a lateral extension far below the lithography limit is made possible.