Abstract: An apparatus (100) for fabricating a semiconductor thin film includes: substrate surface pretreatment means (101) for pretreating a surface of a substrate; organic layer coating means (102) for coating, with an organic layer, the substrate thus pretreated; focused light irradiation means (103) for irradiating, with focused light, the substrate coated with the organic layer, and for forming a growth-mask layer while controlling layer thickness; first thin film growth means (104) for selectively growing a semiconductor thin film over an area around the growth-mask layer; substrate surface treatment means (105) for, after exposing the surface of the substrate by removing the growth-mask layer, modifying the exposed surface of the substrate; and second thin film growth means (106) for further growing the semiconductor thin film and growing a semiconductor thin film over the modified surface of the substrate.

Abstract: A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.

Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.

Abstract: In a method for growing a nanowire array, a photoresist layer is placed onto a nanowire growth layer configured for growing nanowires therefrom. The photoresist layer is exposed to a coherent light interference pattern that includes periodically alternately spaced dark bands and light bands along a first orientation. The photoresist layer exposed to the coherent light interference pattern along a second orientation, transverse to the first orientation. The photoresist layer developed so as to remove photoresist from areas corresponding to areas of intersection of the dark bands of the interference pattern along the first orientation and the dark bands of the interference pattern along the second orientation, thereby leaving an ordered array of holes passing through the photoresist layer. The photoresist layer and the nanowire growth layer are placed into a nanowire growth environment, thereby growing nanowires from the nanowire growth layer through the array of holes.

Abstract: A method for forming a SnO-containing semiconductor film includes a first step of forming a SnO-containing film; a second step of forming an insulator film composed of an oxide or a nitride on the SnO-containing film to provide a laminated film including the SnO-containing film and the insulator film; and a third step of subjecting the laminated film to a heat treatment.

Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.

Abstract: An electric-field-sensitive element (1) includes: an optical function layer (5) that includes a metal oxide selected from the group consisting of tin dioxide, titanium dioxide and zinc oxide, and an insulating material covering the metal oxide, the optical function layer (5) having a visible light transmittance that changes through application of an electric field; and a first and second electrode layer (7, 9) that sandwich the optical function layer (5) therebetween.

Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.

Abstract: A method of forming a metal telluride (MTe) film on a base where M is Cd and optionally additionally may include at least one of Zn, Hg, Mn and Mg, involves depositing a Te-rich precursor layer on a base and reaction of the Te-rich precursor layer with an M-containing material at elevated temperature. The Te-rich precursor film is one of a MTex compound film with an x value larger than 1, a composite film comprising MTe and Te, and a composite film comprising a MTex compound film with an x value larger than 1. In a preferred embodiment the Te-rich precursor layer is electrodeposited. In another preferred embodiment both the Te-rich precursor layer and the M-containing material are electrodeposited.

Abstract: The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

Abstract: Disclosed herein is a method for production of a titanium dioxide composite, the method including a step of preparing titanium dioxide nanowires, a step of dipping the titanium dioxide nanowires in a solution containing titanium oxysulfate and urea, thereby forming titanium dioxide fine particles on the surface of the titanium dioxide nanowires, and a step of recovering the titanium dioxide nanowires having the titanium dioxide fine particles formed on the surface thereof.

Abstract: A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern.

Abstract: A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolation (STI) regions are formed, wherein inner portions of the STI regions are directly over portions of the dislocation-blocking layer, and wherein inner sidewalls of the STI regions contact the dislocation-blocking layer. A second recess is formed by removing a portion of the dislocation-blocking layer between two of the inner sidewalls of the STI regions, with the two inner sidewalls facing each other. A semiconductor region is epitaxially grown in the second recess.

Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.

Abstract: A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide semiconductor layer is formed by using a resist mask, the resist mask is removed, oxygen is introduced (added) to the oxide semiconductor layer, and heat treatment is performed. The removal of the resist mask, introduction of the oxygen, and heat treatment are performed successively without exposure to the air. Through the oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, whereby the oxide semiconductor layer is highly purified. Chlorine may be introduced to an insulating layer over which the oxide semiconductor layer is formed before formation of the oxide semiconductor layer.

Abstract: A semiconductor device, a thin film transistor, and a method for producing the same capable of decreasing the management cost, and capable of decreasing the production steps to reduce the production cost are proposed. A method for producing a thin film transistor 2 provided with a semiconductor which is composed of a prescribed material and serves as an active layer 41 and a conductor which is composed of a material having the same composition as that of the prescribed material and serves as at least one of a source electrode 51, a drain electrode 53 and a pixel electrode 55, which includes the steps of simultaneously forming into a film an object to be processed and a conductor (a source electrode 51, a source wire 52, a drain electrode 53, a drain wire 54 and a pixel electrode 55) which are composed of the amorphous prescribed material, followed by simultaneous shaping, and crystallizing the object to be processed which has been shaped to allow it to be the active layer 41.

Abstract: A plasma hydrogenated region in the dielectric layer of a semiconductor thin film transistor (TFT) structure improves the stability of the TFT. The TFT is a multilayer structure including an electrode, a dielectric layer disposed on the electrode, and a metal oxide semiconductor on the dielectric. Exposure of the dielectric layer to a hydrogen containing plasma prior to deposition of the semiconductor produces a plasma hydrogenated region at the semiconductor-dielectric interface. The plasma hydrogenated region incorporates hydrogen which decreases in concentration from semiconductor/dielectric interface into the bulk of one or both of the dielectric layer and the semiconductor layer.

Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.

Abstract: A field effect transistor including: a substrate, and at least gate electrode, a gate insulating film, a semiconductor layer, a protective layer for the semiconductor layer, a source electrode and a drain electrode provided on the substrate, wherein the source electrode and the drain electrode are connected with the semiconductor layer therebetween, the gate insulating film is between the gate electrode and the semiconductor layer, the protective layer is on at least one surface of the semiconductor layer, the semiconductor layer includes an oxide containing In atoms, Sn atoms and Zn atoms, the atomic composition ratio of Zn/(In+Sn+Zn) is 25 atom % or more and 75 atom % or less, and the atomic composition ratio of Sn/(In+Sn+Zn) is less than 50 atom %.

Abstract: A method of manufacturing a low defect density GaN material comprising at least two steps of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially competent layer under first growing conditions selected to induce island features formation, followed by (b.) a second step of growing an epitaxial layer of GaN under second growing conditions selected to enhance lateral growth until coalescence.

Abstract: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.

Abstract: Provided is a susceptor 13 for manufacturing an epitaxial wafer, comprising a mesh-like groove 13b on a mount face on which a silicon substrate W is to be mounted, wherein a coating H of silicon carbide is formed on the mount face, and the coating has a surface roughness of 1 ?m or more in centerline average roughness Ra and a maximum height of a protrusion 13p generated in forming the coating H of 5 ?m or less. Thus, defects such as warping and slip as well as adhesion of the silicon substrate to the susceptor are prevented.

Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.

Abstract: The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution.

Abstract: According to an embodiment, the present invention provide a method for fabricating a copper indium diselenide semiconductor film using a self cleaning furnace. The method includes transferring a plurality of substrates into a furnace, the furnace comprising a processing region and at least one end cap region disengageably coupled to the processing region, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5, each of the substrates having a copper and indium composite structure.

Abstract: A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.

Abstract: Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.

Abstract: A thin film transistor including a gate electrode, a gate-insulating film, an oxide semiconductor film in contact with the gate-insulating film, and source and drain electrodes which connect to the oxide semiconductor film and are separated with a channel part therebetween, wherein the oxide semiconductor film comprises a crystalline indium oxide which includes hydrogen element, and the content of the hydrogen element contained in the oxide semiconductor film is 0.1 at % to 5 at % relative to all elements which form the oxide semiconductor film.

Abstract: [Object] To provide a sputtering apparatus, a thin-film forming method, and a manufacturing method for a field effect transistor, which are capable of reducing damage of a base layer. [Solving Means] The sputtering apparatus 100 includes a conveying mechanism, a first target Tc1, a second target (Tc2 to Tc5), and a sputtering means. The conveying mechanism conveys a supporting portion, which is arranged in an inside of a vacuum chamber and supports a substrate, linearly along a conveying surface parallel to the surface to be processed of the substrate. The first target Tc1 is opposed to the conveying surface with a first space therebetween. The second target (Tc2 to Tc5) is arranged on a downstream side in a conveying direction of the substrate with respect to the first target Tc1, and is opposed to the conveying surface with a second space smaller than the first space therebetween. The sputtering means sputters each target.

Abstract: The present invention relates to formulations comprising a) at least two different ZnO cubanes of which at least one ZnO cubane is present in solid form under SATP conditions and at least one ZnO cubane is present in liquid form under SATP conditions, and b) at least one solvent, to processes for producing semiconductive ZnO layers from these formulations, to the use of the formulations for producing electronic components and to the electronic components themselves.

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Abstract: A method of fabricating a sensor comprising a nanowire on a support substrate with a first semiconductor layer arranged on the support substrate is disclosed. The method comprises forming a fin structure from the first semiconductor layer, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing at least the fin portion of the fin structure thereby forming the nanowire being surrounded by a first layer of oxide; and forming an insulating layer above the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. A nanowire sensor is also disclosed.

Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.

Abstract: Precursor compositions containing copper and selenium suitable for deposition on a substrate to form thin films suitable for semi-conductor applications. Methods of forming the precursor compositions using primary amine solvents and methods of forming the thin films wherein the selection of temperature and duration of heating controls the formation of a targeted species of copper selenide.

Abstract: A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other.

Abstract: Phase transition devices may include a functional layer made of functional material that can undergo a change in conductance in response to an external stimulus such as an electric or magnetic or optical field, or heat. The functional material transitions between a conducting state and a non-conducting state, upon application of the external stimulus. A capacitive device may include a functional layer between a top electrode and a bottom electrode, and a dielectric layer between the functional layer and the top electrode. A three terminal phase transition switch may include a functional layer, for example a conductive oxide channel, deposited between a source and a drain, and a gate dielectric layer and a gate electrode deposited on the functional layer. An array of phase transition switches and/or capacitive devices may be formed on a substrate, which may be made of inexpensive flexible material.

Abstract: A method of manufacturing an organic electronic device, the method comprising: providing a substrate; forming a well-defining structure over the substrate; and depositing a solution of organic semiconductive material and/or organic conductive material in wells defined by the well-defining structure, wherein the well-defining structure is formed by depositing a solution comprising a mixture of a first insulating material and a second insulating material, the second insulating material having a lower wettability than the first insulating material, and allowing the first and second insulating materials to at least partially phase separate wherein the second insulating material phase separates in a direction away from the substrate.

Abstract: A humidity sensor of capacitive type, a device for detecting or measuring humidity including the sensor, and a method to fabricate the sensor. The humidity sensor includes at least one nanoporous dielectric material positioned between at least one first electrode of a capacitor and at least one second electrode of the capacitor.

Abstract: A method for forming emitter layer of a solar cell includes preparing a substrate including a first impurity of a first conductive type, diffusing a second impurity of a second conductive type opposite to the first conductive type in the substrate to form a first emitter portion of the emitter layer in the substrate, and selectively heating a portion of the first emitter portion, which corresponds to a position for forming at least one electrode, to form a second emitter portion.

Abstract: A method of thin film epitaxial growth using atomic layer deposition is provided by introducing a first deposition precursor and a second deposition precursor into a chamber after a vent valve connected between the chamber and a vacuum pump is closed. The chamber is maintained in a thermal equilibrium state and a constant pressure as a result of keeping the first deposition precursor and the second deposition precursor inside the chamber thereby reducing deposition precursors consumption and achieving thin film epitaxial growth on the substrate.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract: The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.

Abstract: A method for forming a thin-film transistor (TFT) includes providing a substrate, forming a first patterned conducting layer on the substrate, forming an organic dielectric layer on the first patterned conducting layer and the substrate, forming a seeding layer on the organic dielectric layer, using the seeding layer as a crystal growing base to form an inorganic semiconductor layer on the seeding layer, and forming a second patterned conducting layer on the inorganic semiconductor layer.

Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.

Abstract: Systems, methods, and products made by a deposition process are shown and described. A work piece is supported in a main deposition chamber so that the work piece is positioned above each container of deposition material as the container is moved into and out of the deposition chamber. One or more containers are sequentially moved from each of a plurality of auxiliary chambers into and out of the deposition chamber so as to deposit material from each of the containers onto the work piece in a sequential manner.

Abstract: A method of forming a metal oxide film, which can lower a temperature of a heat treatment of a substrate and also can form a metal oxide film having a low resistance value without limiting the kind of the metal oxide film to be formed. The method of forming a metal oxide film includes (A) converting a solution containing a metal into mist, (B) heating a substrate, and (C) supplying the solution converted into mist, and ozone to a first main surface of the substrate under heating.

Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

Abstract: A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

Abstract: A Group III nitride semiconductor substrate is provided, with diameter of 25 mm or more and thickness of 250 ?m or more, wherein in at least an outer edge side part of an outer edge part within 5 mm from an outer edge of the group III nitride semiconductor substrate, stress within a main surface of the group III nitride semiconductor substrate works as a tensile stress, with the tensile stress becoming relatively greater compared to that of a center side part from the outer edge side part of the group III nitride semiconductor substrate.