Deposition Of Semiconductor Material On Substrate, E.g., Epitaxial Growth (epo) Patents (Class 257/E21.461)
E Subclasses
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Patent number: 7732306Abstract: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.Type: GrantFiled: July 25, 2008Date of Patent: June 8, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Chantal Arena, Subhash Mahajan, Ranjan Datta
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Publication number: 20100133656Abstract: A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.Type: ApplicationFiled: December 3, 2008Publication date: June 3, 2010Applicant: United States Government as represented by the Secretary of the ArmyInventors: CARL EMMETT HAGER, IV, MICHAEL ANDREW DERENGE, KENNETH ANDREW JONES
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Publication number: 20100136743Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.Type: ApplicationFiled: February 3, 2010Publication date: June 3, 2010Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
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Publication number: 20100126568Abstract: Disclosed is a nanostructure including a first set of nanowires formed from filling a plurality of voids of a template. The nanostructure also includes a second set of nanowires formed from filling a plurality of spaces created when the template is removed, such that the second set of nanowires encases the first set of nanowires. Several methods are also disclosed. In one embodiment, a method of fabricating a nanostructure including nanowires is disclosed. The method may include forming a first set of nanowires in a template, removing a first portion of the template, thereby creating spaces between the first set of nanowires, forming a second set of nanowires in the spaces between the first set of nanowires, and removing a second portion of the template.Type: ApplicationFiled: January 14, 2010Publication date: May 27, 2010Inventors: Charles Elijah May, Vijay Pal Singh, Suresh KS Rajaputra
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Publication number: 20100123129Abstract: Mg is doped in a ZnO-containing semiconductor layer in a concentration range from 1×1017 cm?3 to 2×1020 cm?3.Type: ApplicationFiled: November 3, 2009Publication date: May 20, 2010Applicant: Stanley Electric Co., Ltd.Inventors: Tomofumi Yamamuro, Hiroyuki Kato
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Publication number: 20100120220Abstract: A method for fabricating a semiconductor device includes: forming a stack structure including pillar regions whose upper portion has a wider width than a lower portion over a substrate, the lower portion including at least a conductive layer; forming a gate insulation layer on sidewalls of the pillar regions; forming active pillars to gap-fill the pillar regions; and forming vertical gates that serve as both gate electrode and word lines by selectively etching the conductive layer.Type: ApplicationFiled: June 26, 2009Publication date: May 13, 2010Inventor: Young-Kyun Jung
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Publication number: 20100120218Abstract: A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.Type: ApplicationFiled: June 26, 2009Publication date: May 13, 2010Inventor: Myung-Ok Kim
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Publication number: 20100120197Abstract: A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. during fabrication.Type: ApplicationFiled: January 20, 2010Publication date: May 13, 2010Inventors: David H. Levy, Andrea C. Scuderi, Lyn M. Irving
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Publication number: 20100120192Abstract: A method for preparing III-VI2 nanoparticles and a thin film of polycrystalline light absorber layers. The method for preparing I-III-VI2 nanoparticles comprises the steps of: (a1) preparing a mixed solution by mixing each element from groups I, III and VI in the periodic table with a solvent; (a2) sonicating the mixed solution; (a3) separating the solvent from the sonicated mixed solution; and (a4) drying the product resulted from the above step (a3) to obtain nanoparticles.Type: ApplicationFiled: June 17, 2008Publication date: May 13, 2010Applicant: SUNGKYUNKWAN UNIVERSITYInventors: Duk-Young Jung, Jae Eok Han, Juyeon Chang
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Publication number: 20100109035Abstract: The present invention provides a compound semiconductor light emitting device including: an Si—Al substrate; protection layers formed on top and bottom surfaces of the Si—Al substrate; and a p-type semiconductor layer, an active layer, and an n-type semiconductor layer which are sequentially stacked on the protection layer formed on the top surface of the Si—Al substrate, and a method for manufacturing the same.Type: ApplicationFiled: April 3, 2009Publication date: May 6, 2010Inventors: Myong Soo CHO, Ki Yeol PARK, Pun Jae Choi
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Patent number: 7704888Abstract: Methods for removing photoresist from semiconductor structures are provided. In an exemplary embodiment, a method for removing photoresist from a semiconductor structure having a high-k dielectric material layer overlying a substrate comprises depositing a photoresist overlying the high-k dielectric material layer and patterning the photoresist. The temperature of the substrate is adjusted to a temperature of no less than about 400° C. and hydrogen gas is excited to form a hydrogen plasma of excited H and H2 species. The photoresist is subjected to the excited H and H2 species from the hydrogen plasma.Type: GrantFiled: January 23, 2007Date of Patent: April 27, 2010Assignee: Globalfoundries Inc.Inventor: Richard J. Carter
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Patent number: 7696019Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.Type: GrantFiled: March 9, 2006Date of Patent: April 13, 2010Assignee: Infineon Technologies AGInventor: Jin-Ping Han
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Publication number: 20100084664Abstract: A semiconductor structure includes a substrate which may be formed from a ZnS single crystal of wurtzite (2H) structure with a predetermined crystal orientation, and which has a first surface and a second surface. The structure includes a layer of a group III-nitride crystalline material deposited as an epitaxial layer on the first surface of the substrate. In one embodiment, the group III-nitride deposit is epitaxially grown using a MOCVD (or MOVPE) technique or a HVPE technique or a combination thereof. There may be a mask and/or a buffer layer on the first surface and/or a protective layer on the second surface.Type: ApplicationFiled: October 6, 2009Publication date: April 8, 2010Applicant: FAIRFIELD CRYSTAL TECHNOLOGY, LLCInventor: Shaoping Wang
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Manufacturing method of nitride substrate, nitride substrate, and nitride-based semiconductor device
Patent number: 7691732Abstract: A manufacturing method of a nitride substrate includes the steps of preparing a ground substrate; forming a mask on the ground substrate; placing the ground substrate in a reactor, and heating the ground substrate to a temperature of 850° C. to 1100° C. In the step of heating the ground substrate, HCl and NH3 are supplied into the reactor so that partial pressure PHCl satisfies (1.5+0.0005 p) kPa?PHCl?(4+0.0005 p) kPa and partial pressure PNH3 satisfies (15?0.0009 p) kPa?PNH3?(26?0.0017 p) kPa, whereby an AlxGayIn1-x-yN crystal (0?x<1, 0<y?1) is grown, and whereby a ridge-valley structure including a plurality of ridges and valleys parallel to one another is formed. The AlxGayIn1-x-yN crystal is grown so that the ridge-valley structure is not buried while a height of the valleys from the ground substrate is allowed to exceed 2.5 (p?s).Type: GrantFiled: June 18, 2008Date of Patent: April 6, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takuji Okahisa, Hideaki Nakahata, Koji Uematsu -
Patent number: 7682939Abstract: This invention relates to a method for producing group IB-IIA-VIA quaternary or higher alloy semiconductor films wherein the method comprises the steps of (i) providing a metal film comprising a mixture of group IB and group IIIA metals; (ii) heat treating the metal film in the presence of a source of a first group VIA element (said first group VIA element hereinafter being referred to as VIA1) under conditions to form a first film comprising a mixture of at least one binary alloy selected from the group consisting of a group IB-VIA1 alloy and a group IIIA-VIA1 alloy and at least one group IB-IIIA-VIA1 ternary alloy (iii) optionally heat treating the first film in the presence of a source of a second group VIA element (said second group VI element hereinafter being referred to as VIA2) under conditions to convert the first film into a second film comprising at least one alloy selected from the group consisting of a group IB-VIA1-VIA2 alloy and a group IIIA-VIA1-VIA2 alloy; and the at least one group IB-III-VIType: GrantFiled: August 13, 2004Date of Patent: March 23, 2010Assignee: University of JohannesburgInventor: Vivian Alberts
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Patent number: 7682940Abstract: In a first aspect, a first method of forming an epitaxial film on a substrate is provided. The first method includes (a) providing a substrate; (b) exposing the substrate to at least a silicon source so as to form an epitaxial film on at least a portion of the substrate; and (c) exposing the substrate to HCl and Cl2 so as to etch the epitaxial film and any other films formed during step (b). Numerous other aspects are provided.Type: GrantFiled: September 14, 2005Date of Patent: March 23, 2010Assignee: Applied Materials, Inc.Inventors: Zhiyuan Ye, Yihwan Kim, Xiaowei Li, Ali Zojaji, Nicholas C. Dalida, Jinsong Tang, Xiao Chen, Arkadii V. Samoilov
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Publication number: 20100055832Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.Type: ApplicationFiled: August 28, 2009Publication date: March 4, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kengo AKIMOTO, Masashi TSUBUKU
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Publication number: 20100051950Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.Type: ApplicationFiled: December 17, 2008Publication date: March 4, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Ming-Wei Sun, Chih-Wei Chao
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Publication number: 20100029066Abstract: An aspect of the present invention relates to a susceptor comprising a counterbored groove receiving a semiconductor wafer in the course of manufacturing an epitaxial wafer by vapor phase growing an epitaxial layer on a surface of the semiconductor wafer, wherein a lateral wall of the counterbored groove is comprised of at least one flat portion and at least one protruding portion being higher than the flat portion, and a height of the flat portion is equal to or greater than a thickness of the semiconductor wafer.Type: ApplicationFiled: July 30, 2009Publication date: February 4, 2010Applicant: SUMCO CORPORATIONInventor: Junji MIYASHITA
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Publication number: 20100001334Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.Type: ApplicationFiled: October 27, 2008Publication date: January 7, 2010Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Fumitake Mieno
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Publication number: 20090320914Abstract: Provided are a dye-sensitized solar cell and a method of fabricating the same. The dye-sensitized solar cell includes an electrode structure including a conductive layer having pores that are regularly arranged, a semiconductor oxide layer disposed on a surface of the conductive layer, and a dye layer disposed on a surface of the semiconductor oxide layer.Type: ApplicationFiled: May 9, 2008Publication date: December 31, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Ho-Gyeong YUN, Yong-Seok JUN, Man-Gu KANG, Seung-Yup LEE, Hunkyun PAK, Jong-Hyeok PARK, Jong-Dae KIM
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Publication number: 20090325336Abstract: A method of printing an ink on a wafer surface configured with a set of non-rounded peaks and a set of non-rounded valleys is disclosed. The method includes exposing the wafer including at least some non-rounded peaks and at least some of the non-rounded valleys in a region to an etchant. The method further includes depositing the ink on the region, wherein a set of rounded peaks and a set of rounded valleys are formed.Type: ApplicationFiled: April 24, 2008Publication date: December 31, 2009Inventors: Malcolm Abbott, Maxim Kelman, Karel Vanheusden
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Publication number: 20090314210Abstract: A susceptor for use in an epitaxial growth apparatus and method where a plurality of circular through-holes are formed in the bottom wall of a pocket in an outer peripheral region a distance of up to about ½ the radius toward the center of the circular bottom wall. The total opening surface area of these through-holes is 0.05 to 55% of the surface area of the bottom wall. The opening surface area of each of the through-holes provided at this outer peripheral region is 0.2 to 3.2 mm2 and the density of the through-holes is 0.25 to 25 per cm2. After a semiconductor wafer is mounted in the pocket, epitaxial growth is carried out while source gas and carrier gas (i.e., reactive gas) is made to flow on the upper surface side of the susceptor and carrier gas is made to flow on the lower surface side.Type: ApplicationFiled: August 25, 2009Publication date: December 24, 2009Inventors: Masayuki Ishibashi, John F. Krueger, Takayuki Dohi, Daizo Horie, Takashi Fujikawa
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Publication number: 20090305452Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.Type: ApplicationFiled: February 27, 2009Publication date: December 10, 2009Inventors: Edward Sargent, Gerasimos Konstantatos, Larissa Levina, Ian Howard, Ethan J.D. Klem, Jason Clifford
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Publication number: 20090305437Abstract: A method of forming an integrated circuit layer material is described, comprising depositing a layer of templates on a substrate, said template including a first binding site having an affinity for the substrate, a second binding site having an affinity for a target integrated circuit material and a protecting material coupled to the second binding site via a labile linkage to prevent the binding site from binding to the target integrated circuit material; exposing the template to an external stimulus to degrade the labile linkage; removing the protecting material; and binding the integrated circuit material to the second binding site.Type: ApplicationFiled: March 8, 2007Publication date: December 10, 2009Applicant: CAMBRIOS TECHNOLOGIES CORPORATIONInventors: Pierre-Marc Allemand, Manfred Heidecker, Gregory L. Kirk, Xina Quan, Cheng-I Wang
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Publication number: 20090298226Abstract: During a process of forming an active layer of a semiconductor device using a ZnO film, the ZnO film is laser-annealed with an ultraviolet pulsed laser to reduce the resistance of the film, and then oxidation treatment is applied to increase the specific resistance value at a channel portion of the ZnO film, which once has excessively low resistance after the laser annealing, to 103?·cm or more.Type: ApplicationFiled: May 29, 2009Publication date: December 3, 2009Applicant: FUJIFILM CORPORATIONInventors: Kenichi Umeda, Atsushi Tanaka, Kohei Higashi, Maki Nangu
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Publication number: 20090294758Abstract: A ZnO-containing semiconductor layer, doped with Se, has an emission peak wavelength in visual light and has a band gap equivalent to a band gap of ZnO.Type: ApplicationFiled: August 13, 2009Publication date: December 3, 2009Applicant: STANLEY ELECTRIC CO., LTD.Inventors: Akio OGAWA, Michihiro Sano, Hiroyuki Kato, Naochika Horio, Hiroshi Kotani, Tomofumi Yamamuro
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Publication number: 20090289249Abstract: Disclosed is an oxide semiconductor having an amorphous structure, wherein higher mobility and reduced carrier concentration are achieved. Also disclosed are a thin film transistor, a method for producing the oxide semiconductor, and a method for producing the thin film transistor. Specifically disclosed is an oxide semiconductor which is characterized by being composed of an amorphous oxide represented by the following a general formula: Inx+1MZny+1SnzO(4+1.5x+y+2z) (wherein M is Ga or Al, 0?x?1, ?0.2?y?1.2, z?0.4 and 0.5?(x+y)/z?3). This oxide semiconductor is preferably subjected to a heat treatment in an oxidizing gas atmosphere after film formation. Also specifically disclosed is a thin film transistor which is characterized by comprising the oxide semiconductor.Type: ApplicationFiled: May 25, 2007Publication date: November 26, 2009Applicant: FUJI ELECTRIC HOLDINGS.,LTD.Inventors: Hisato Kato, Haruo Kawakami, Nobuyuki Sekine, Kyoko Kato
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Patent number: 7618836Abstract: A method for manufacturing a semiconductor optical device comprises: forming a groove on a first semiconductor layer; forming a second semiconductor layer containing aluminum in the groove; forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; forming an insulating layer on the third semiconductor layer covering the region opposite the second semiconductor layer; forming a stripe-shaped structure by etching the first semiconductor layer and the third semiconductor layer without exposing the second semiconductor layer, using the insulating layer as a mask; and burying the stripe-shaped structure with burying layers.Type: GrantFiled: May 1, 2008Date of Patent: November 17, 2009Assignee: Mitsubishi Electric CorporationInventor: Go Sakaino
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Publication number: 20090280612Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: ApplicationFiled: July 17, 2009Publication date: November 12, 2009Applicant: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090280600Abstract: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having a source electrode 6, a drain electrode 5, a gate electrode 4, a gate insulating film 3, and a channel layer 2, an amorphous oxide having an electron carrier concentration less than 1018/cm3 is used in the channel layer 2.Type: ApplicationFiled: July 16, 2009Publication date: November 12, 2009Applicant: Japan Science and Technology AgencyInventors: Hideo HOSONO, Masahiro HIRANO, Hiromichi OTA, Toshio KAMIYA, Kenji NOMURA
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Patent number: 7615390Abstract: The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus (10) comprising a chamber (12) having a gas input port (14) and a gas output port (16), and means (18) for mounting a silicon substrate within the chamber (12), said apparatus further including a gas source connected to the input port and arranged to provide nitrogen or a noble gas as a carrier gas.Type: GrantFiled: August 13, 2003Date of Patent: November 10, 2009Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Mathieu Rosa Jozef Caymax
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Patent number: 7611951Abstract: Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects.Type: GrantFiled: September 8, 2006Date of Patent: November 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Tetsuji Ueno, Hwa-Sung Rhee, Ho Lee
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Publication number: 20090263959Abstract: A device layer is formed on at least the upper surface of a prime wafer by an epitaxial growth method. Then, a protective film is formed to cover at least the device layer. The lower surface of the prime wafer is ground to have a flat lower surface.Type: ApplicationFiled: March 13, 2009Publication date: October 22, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Masatsugu Desaki
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Patent number: 7605012Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: GrantFiled: June 27, 2005Date of Patent: October 20, 2009Assignees: National Institute of Advanced Industrial Science & Tech., Rohm Co., Ltd.Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara
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Publication number: 20090250748Abstract: A semiconductor device and method of fabricating the same includes preparing a substrate, forming a plurality of conductive layer patterns on the substrate, forming a gate insulation layer on sidewalls of the conductive layer patterns, forming a pillar neck pattern between the conductive layer patterns, forming a pillar head over the pillar neck pattern and the conductive layer patterns, and forming a gate electrode surrounding the pillar neck pattern and forming a pillar head pattern by selectively etching the conductive layer patterns and the pillar head formed over the pillar neck pattern.Type: ApplicationFiled: December 23, 2008Publication date: October 8, 2009Applicant: Hynix Semiconductor Inc.Inventor: Myung-Ok Kim
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Publication number: 20090252974Abstract: This invention generally relates to a process for suppressing silicon self-interstitial diffusion near the substrate/epitaxial layer interface of an epitaxial silicon wafer having a heavily doped silicon substrate and a lightly doped silicon epitaxial layer. Interstitial diffusion into the epitaxial layer is suppressed by a silicon self-interstitial sink layer comprising dislocation loops.Type: ApplicationFiled: June 17, 2009Publication date: October 8, 2009Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Robert J. Falster, Vladimir V. Voronkov, Luca Moiraghi, DongMyun Lee, Chanrae Cho, Marco Ravani
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Patent number: 7598178Abstract: The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius and a pressure greater than about 1 Torr so as to form an epitaxial film on at least a portion of the substrate. Then, the substrate is exposed to an etchant so as to etch the epitaxial film and any other films formed during the deposition. The deposition and etching may be repeated until a film of a desired thickness is achieved. Numerous other aspects are disclosed.Type: GrantFiled: March 23, 2007Date of Patent: October 6, 2009Assignee: Applied Materials, Inc.Inventors: Arkadii V. Samoilov, Rohini Kodali, Ali Zojaji, Yihwan Kim
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Publication number: 20090224368Abstract: A semiconductor device, comprising a silicon layer, an n-type field-effect transistor (NFET) disposed in and on a silicon layer, and a p-type field-effect transistor (PFET) disposed in and on the silicon layer, wherein the PFET includes a boron-doped silicon-germanium layer disposed on the silicon layer. Also, a method for manufacturing a semiconductor device, comprising forming a first conductive layer over a p-well of a silicon layer, forming a second conductive layer over an n-well of the silicon layer, implanting fluorine ions into both the p-well and the n-well, exposing both the p-well and the n-well to ammonium hydroxide and peroxide, and epitaxially growing a boron-doped silicon-germanium layer on the silicon layer.Type: ApplicationFiled: March 3, 2009Publication date: September 10, 2009Applicant: Toshiba America electronic Components, Inc.Inventor: Gaku Sudo
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Publication number: 20090221131Abstract: Provided is a method for easily preparing a substrate comprising a monocrystalline film thereon or thereabove with almost no crystal defects without using a special substrate.Type: ApplicationFiled: February 24, 2009Publication date: September 3, 2009Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Yoshihiro Kubota, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Shoji Akiyama, Yoshihiro Nojima
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Publication number: 20090215209Abstract: Methods for depositing material and/or nanomaterial are disclosed. Also disclosed are methods of making devices including nanomaterials, systems useful for depositing materials and/or nanomaterials, surface treated articles for depositing material and/or nanomaterial onto a substrate, and surface treated transfer surfaces.Type: ApplicationFiled: October 7, 2008Publication date: August 27, 2009Inventors: Maria J. Anc, Seth Coe-Sullivan, LeeAnn Kim, Moungi G. Bawendi
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Publication number: 20090212333Abstract: A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminum is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminum to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity.Type: ApplicationFiled: February 12, 2009Publication date: August 27, 2009Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble) SAS, Commissariat a L'Energie AtomiqueInventors: Emilie Bernard, Bernard Guillaumot, Philippe Coronel, Christian Vizioz
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Publication number: 20090215249Abstract: Methods for forming embedded epitaxial layers containing silicon and carbon are disclosed. Specific embodiments pertain to the formation embedded epitaxial layers containing silicon and carbon on silicon wafers. In specific embodiments an epitaxial layer of silicon and carbon is non-selectively formed on a substrate or silicon wafer, portions of this layer are removed to expose the underlying substrate or silicon wafer, and an epitaxial layer containing silicon is formed on the exposed substrate or silicon wafers. In specific embodiments, gates are formed on the resulting silicon-containing epitaxial layers.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Inventors: John Boland, Zhiyuan Ye, Yihwan Kim
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Publication number: 20090200534Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.Type: ApplicationFiled: February 7, 2008Publication date: August 13, 2009Applicants: IBM CORPORATION, MACRONIX INTERNATIONAL CO., LTD., QIMONDA AGInventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
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Publication number: 20090197399Abstract: Provided are a method of growing a group III-V compound semiconductor, and method of manufacturing a light-emitting device and an electron device, in which risks are reduced and nitrogen can be efficiently supplied at low temperatures. The method of growing a group III-V compound semiconductor includes the following processes. First, gas containing at least one selected from the group consisting of monomethylamine and monoethylamine is prepared as a nitrogen raw material. Then, the group III-V compound semiconductor is grown using the gas by vapor phase growth.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Takao Nakamura, Masaki Ueno, Toshio Ueda, Eiryo Takasuka, Yasuhiko Senda
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Publication number: 20090186437Abstract: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.Type: ApplicationFiled: March 26, 2009Publication date: July 23, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Kengo Akimoto
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Publication number: 20090184311Abstract: Electrodeposition is used to deposit nanowires in a controlled fashion with accurate placement and orientation. A substrate is provided with a mesa having electrically conductive sidewalls. The substrate is immersed in an electroplating solution having a dispersion of nanowires, and metal is electroplated onto the sidewalls of the mesa. During electrodeposition, nanowires are incorporated and partially embedded in the deposited metal film. The nanowires will tend to be parallel with the substrate. Additionally electrodes can be deposited to provide electrical contact with the free ends of the nanowires. In this way, electrical connections can be provided to nanowires in a controlled, reproducible manner. The deposited nanowires can be used in a multitude of devices.Type: ApplicationFiled: November 12, 2008Publication date: July 23, 2009Inventor: Dan Steinberg
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Publication number: 20090179259Abstract: A method of forming a semiconductor device on a heavily doped P-type (110) semiconductor layer over a metal substrate includes providing a first support substrate and forming a P-type heavily doped (110) silicon layer overlying the first support substrate. At least a top layer of the first support substrate is removable by a selective etching process with respect to the P-type heavily doped (110) silicon layer. A vertical semiconductor device structure is formed in and over the (110) silicon layer. The vertical device structure includes a top metal layer and is characterized by a current conduction in a <110> direction.Type: ApplicationFiled: July 16, 2008Publication date: July 16, 2009Inventors: QI WANG, Minhua Li, Yuri Sokolov
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Patent number: 7560352Abstract: A method for epitaxially forming a silicon-containing material on a substrate surface utilizes a halogen containing gas as both an etching gas as well as a carrier gas through adjustments of the process chamber temperature and pressure. It is beneficial to utilize HCl as the halogen containing gas because converting HCl from a carrier gas to an etching gas can easily be performed by adjusting the chamber pressure.Type: GrantFiled: March 17, 2006Date of Patent: July 14, 2009Assignee: Applied Materials, Inc.Inventors: David K. Carlson, Satheesh Kuppurao, Errol Antonio C. Sanchez, Howard Beckford, Yihwan Kim
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Patent number: 7560296Abstract: A method of manufacturing a low defect density GaN material comprising at least two step of growing epitaxial layers of GaN with differences in growing conditions, (a.) a first step of growing an epitaxial layer GaN on an epitaxially compentent layer under first growing conditions selected to induce island features formation, followed by (b.) a second step of growing an epitaxial layer of GaN under second growing conditions selected to enhance lateral growth until coalescence.Type: GrantFiled: September 11, 2006Date of Patent: July 14, 2009Assignee: LumilogInventors: Eric Frayssinet, Bernard Beaumont, Jean-Pierre Faurie, Pierre Gibart