Abstract: A substrate processing apparatus has a cup part for receiving processing liquid which is applied from a processing liquid applying part and is splashed from a substrate, and the cup part is formed of electrical insulation material. Hydrophilic treatment is performed on an outer annular surface of the cup part and water is held on the outer annular surface of the cup part while processing the substrate. With this structure, charged potential of the cup part generated in splashing of pure water can be suppressed by the water held on the outer annular surface, without greatly increasing the manufacturing cost of the substrate processing apparatus by forming the cup part with special conductive material. As a result, it is possible to prevent electric discharge from occurring on the substrate due to induction charging of the substrate, in application of the processing liquid onto the substrate.

Abstract: An electrode (3i) of a radiofrequency parallel plate plasma reactor includes an electrode surface of a multitude of surfaces of metal members (28) which reside on dielectric spacing members (29), whereby the metal members (28) are mounted in an electrically floating manner. The dielectric members (29) are mounted, opposite to the metal members (28), upon a metal Rf supply body (14a).

Abstract: A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.

Abstract: Provided is a method of manufacturing a sensor structure, where vertically-well-aligned nanotubes are formed and the sensor structure having an excellent performance can be manufactured at the room temperature at low cost by using the nanotubes. The method of manufacturing a sensor structure includes: (a) forming a lower electrode on a substrate; (b) forming an organic template having a pore structure on the lower electrode; (c) forming a metal oxide thin film in the organic template; (d) forming a metal oxide nanotube structure, in which nanotubes are vertically aligned and upper portions thereof are connected to each other, by removing the organic template through a dry etching method; and (e) forming an upper electrode on the upper portions of the nanotubes.

Abstract: A method for fabricating a MEMS resonator is provided. A stacked main body including a silicon substrate, a plurality of metallic layers and an isolation layer is formed and has a first etching channel extending from the metallic layers into the silicon substrate. The isolation layer is filled in the first etching channel. The stacked main body also has a predetermined suspended portion. Subsequently, a portion of the isolation layer is removed so that a second etching channel is formed and the remained portion of the isolation layer covers an inner sidewall of the first etching channel. Afterwards, employing the isolation layer that covers the inner sidewall of the first etching channel as a mask, an isotropic etching process through the second etching channel is applied to the silicon substrate, thereby forming the MEMS resonator suspending above the silicon substrate.

Abstract: A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.

Abstract: The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.

Abstract: The present invention includes the steps of: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: The invention provides an epitaxial substrate and fabrication thereof. The epitaxial substrate according to the invention includes a crystalline substrate. In particular, the crystalline substrate has an epitaxial surface which is nano-rugged and non-patterned. The epitaxial substrate according to the invention thereon benefits a compound semiconductor material in growth of epitaxy films with excellent quality. Moreover, the fabrication of the epitaxial substrate according to the invention has advantages of low cost and rapid production.

Abstract: A mixture of perhalogenic acid and sulfuric acid is unexpectedly stable at high temperatures and is effective in stripping photoresists, including difficult to treat ion-implanted photoresists, with short processing times. In use, no decomposition of the mixture is observed up to a temperature of 145° C. In the mixture, the sulfuric acid is highly purified and has a concentration of 96 wt % or greater. The perhalogenic acid is preferably H5IO6.

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.

Abstract: The invention can provide apparatus and methods of processing a substrate in real-time using a switchable quasi-neutral beam system to improve the etch resistance of photoresist layer. In addition, the improved photoresist layer can be used in an etch procedure to more accurately control gate and/or spacer critical dimensions (CDs), to control gate and/or spacer CD uniformity, and to eliminate line edge roughness (LER) and line width roughness (LWR).

Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.

Abstract: A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.

Abstract: Methods of processing substrates having titanium nitride layers are provided. In some embodiments, a method for processing a substrate having a dielectric layer to be etched, a titanium nitride layer above the dielectric layer, and a patterned photoresist layer above the titanium nitride layer, includes etching a pattern into the titanium nitride layer by exposing the titanium nitride layer to a first plasma comprising a chlorine containing gas to form a hard mask; removing titanium nitride etch residues disposed on one or more surfaces of the process chamber and/or substrate by forming a second plasma in the process chamber from a reactive gas comprising at least one of carbon monoxide or carbon dioxide; and etching the dielectric layer through the hard mask with a third plasma comprising a fluorocarbon gas.

Abstract: Surface processing in which the area to be processed is restricted to a predetermined pattern, can be achieved by: (a) providing a layer of a first reagent over a region of the surface to be processed which at least covers an area of the predetermined pattern; (b) providing one or more further reagents which are further reagents required for the processing of the surface; and (c) applying at least one of the further reagents over the region to be processed according to the predetermined pattern; such that the first reagent acts with the one or more of the further reagents to process the surface only in the area of the predetermined pattern. The process is particularly applicable to etching where an etchant having two or more components is used. In that case at least a first etchant component is applied over the surface and at least one further etchant component is applied in the predetermined pattern.

Abstract: A method is provided for anisotropically etching semiconductor materials such as II-VI and III-V semiconductors. The method involves repeated cycles of plasma sputter etching of semiconductor material with a non-reactive gas through an etch mask, followed by passivation of the side walls by plasma polymerization using a polymer former. Using this procedure small pixels in down-converted light-emitting diode devices can be fabricated.

Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.

Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.

Abstract: A layer to be etched is first formed in a substrate. Then, a mask pattern is formed over the layer to be etched. Then, the layer to be etched is wet-etched using the mask pattern as a mask. In the procedure of performing wet etching, the substrate is dipped into an etching bath with the mask pattern downward.

Abstract: A slurry composition for a chemical mechanical processing process includes about 0.05 to about 0.3 percent by weight of a ceria abrasive, about 0.005 to about 0.04 percent by weight of an anionic surfactant, about 0.0005 to about 0.003 percent by weight of a polyoxyethylene-based nonionic surfactant, about 0.2 to about 1.0 percent by weight of a salt of polyacrylic acid having an average molecular weight substantially greater than a molecular weight of the anionic surfactant, and a remainder of water. In addition, a method of polishing an object layer and a method of manufacturing a semiconductor device using the slurry composition are also provided.

Abstract: Provided is a method of manufacturing a sensor structure, where vertically-well-aligned nanotubes are formed and the sensor structure having an excellent performance can be manufactured at the room temperature at low cost by using the nanotubes. The method of manufacturing a sensor structure includes: (a) forming a lower electrode on a substrate; (b) forming an organic template having a pore structure on the lower electrode; (c) forming a metal oxide thin film in the organic template; (d) forming a metal oxide nanotube structure, in which nanotubes are vertically aligned and upper portions thereof are connected to each other, by removing the organic template through a dry etching method; and (e) forming an upper electrode on the upper portions of the nanotubes.

Abstract: Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.

Abstract: A platinum-comprising material is plasma etched by being exposed to a plasma etching chemistry that includes CHCl3, CO2 and O2. In one embodiment, a method of processing a semiconductor substrate in the fabrication of integrated circuitry includes forming metallic platinum-comprising nanoparticles over a material. A portion of the nanoparticles is masked and another portion of the nanoparticles is unmasked. The unmasked portion of the metallic platinum-comprising nanoparticles is plasma etched using a plasma etching chemistry comprising CHCl3, CO2 and O2. Other embodiments are disclosed.

Abstract: There are disclosed a semiconductor device in which a short circuit between an oscillator and a semiconductor substrate is prevented, the semiconductor device being capable of suppressing an increase of fabrication steps, and a method of fabricating the semiconductor device. The semiconductor device includes: a semiconductor substrate, in which a recessed portion is formed on an upper surface, and a semiconductor layer is exposed to a bottom surface of the recessed portion; an oscillator that has a beam-type movable electrode arranged in the recessed portion, the movable electrode having insulating films arranged on side surfaces and lower surface thereof, and is fixed to the semiconductor substrate at a position apart from the movable electrode; and a beam-type fixed electrode that is arranged in the recessed portion so as to be opposed to the movable electrode, and is fixed to the semiconductor substrate so as to be electrically isolated from the movable electrode.

Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.

Abstract: An organic/inorganic hybrid film represented by SiCxHyOz (x>0, y?0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to thereby reform the surface portion. The reformed surface portion is nicely plasma-etched with the etching gas containing fluorine and carbon.

Abstract: A method of manufacturing microstructures is disclosed, the method comprising a applying a mask to substrate; forming a pattern in the mask; processing the substrate according to the pattern; and mechanically removing the mask from the substrate. A polymer mask is disclosed for manufacturing micro scale structure, the polymer mask comprising a thin, preferably ultra thin flexible film. A method of manufacturing an integrated circuit is disclosed, the method comprising forming a plurality of isolated semiconductor devices on a common substrate; and connecting some of the devices. Apparatus for manufacturing microstructures is disclosed comprising: a mechanism for coating a mass substrate to create a structure; a mechanism for removing a mask from the substrate; and processing apparatus.

Abstract: A first material film is formed on a substrate. Linear second material film patterns are formed on the first material film. Spacer patterns are formed on sidewalls of the second material film patterns, and the second material film patterns are removed to expose portions of the first material film between the spacer patterns. The exposed portions of the first material film are removed to form first material film patterns. Third material film patterns are formed in trenches defined by the first material film patterns. Adjacent first portions of the second material film patterns proximate ends of the second material film patterns are separated by a distance less than twice a width of the individual spacer patterns. In some embodiments, the distance separating the adjacent first portions of the second material film patterns is greater than a minimum feature size, and a width of the individual spacer patterns is approximately equal to the minimum feature size.

Abstract: A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.

Abstract: A process for structuring at least one layer as well as an electrical component with structures from the layer are described. The invention states a process to generate at least one structured layer (10A), wherein a mask structure (20) with a first (20A) and second structure (20B) is generated on a layer (10) which is present on a substrate (5). Through this mask structure (20), the first layer (20A) is transferred onto the layer (10) using isotropic structuring processes, and the second structure (20B) is transferred onto the layer (10) using anisotropic structuring processes. The process as per the invention permits the generation of two structures (20A, 20B) in at least a single layer while using a single mask structure.

Abstract: A trench is formed by a process which removes a damage layer formed on a sidewall of a low dielectric constant layer, a process which forms a second protection insulating layer by a chemical vapor deposition (CVD) technique and forms a second concave portion by covering a sidewall of the low dielectric constant layer with the second protection insulating layer, and a process which shapes the second protection insulating layer by etch back so that a trench has a sidewall that the second protection insulating layer is selectively formed on a surface of the low dielectric constant layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. In the method of manufacturing the semiconductor device, a first insulating layer is formed on a semiconductor substrate. A metal line layer and an etch-stop layer are formed over the first insulating layer. The etch-stop layer and the metal line layer are patterned to form a metal line. A second insulating layer is formed on the first insulating layer and the etch-stop layer. A first etch process for etching part of the second insulating layer is performed by using a first etch gas so that the etch-stop layer is exposed. A second etch process for removing the etch-stop layer is performed by using a second etch gas so that the metal line is exposed.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method includes sequentially depositing a polishing stop film and a mask oxide film on a semiconductor substrate, forming a photosensitive film pattern on the mask oxide film to expose a device isolation region, sequentially etching the mask oxide film and the polishing stop film under first and second etching process conditions using the photosensitive film pattern as a mask to form a hard mask pattern, and etching the semiconductor substrate under third etching process conditions using the hard mask pattern to form a trench for a device-isolation film. Advantageously, the method simplifies an overall process without using a spacer and secures a desired margin in the subsequent processes, e.g., gap-filling an insulating material in the trench and chemical mechanical polishing of the insulating material.

Abstract: A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.

Abstract: Methods for etching a metal material layer disposed on a substrate to form features with desired profile and uniform critical dimension (CD) of the features across the substrate. In one embodiment, a method for etching a material layer disposed on a substrate includes providing a substrate having a metal layer disposed on a substrate into an etch reactor, flowing a gas mixture containing at least a halogen containing gas and a passivation gas into the reactor, the passivation gas including a nitrogen containing gas and an unsaturated hydrocarbon gas, wherein the nitrogen gas and the unsaturated hydrocarbon gas and etching the metal layer using a plasma formed from the gas mixture. The CD uniformity could be conveniently, efficiently tuned by the gas ratio, if the concentration of the unsaturated hydrocarbon gas is high enough that the molecular ratio of the unsaturated hydrocarbon gas in the diluent gas times the reactor pressure in milliTorr is greater than 1.25.

Abstract: A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends.

Abstract: A substrate processing method includes performing an etching process on a low dielectric constant film disposed on a substrate, thereby forming a predetermined pattern thereon; denaturing a remaining substance to be soluble in a predetermined liquid after the etching process; dissolving and removing the substance thus denatured, by supplying the predetermined liquid thereon; then, performing a silylation process on a surface of the low dielectric constant film, by supplying a silylation agent thereon, after said dissolving and removing the substance denatured; and baking the substrate after the silylation process.

Abstract: The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein the wiring process is performed without causing disconnection or deflection of the wiring. The invention provides a dry etching method for performing a wiring process on a semiconductor substrate using a plasma etching apparatus, wherein during a step for etching a material 12 to be etched using a mask pattern composed of a photoresist 15 and inorganic films 14 and 13 made of SiN, SiON, SiO and the like formed on the material 12 to be etched, a mixed gas formed of a halogen-based gas such as chlorine-containing gas or bromine-containing gas and at least one fluorine-containing gas selected from a group of fluorine-containing gases composed of CF4, CHF3, SF6 and NF3 is used to reduce the mask pattern and the processing dimension of the material to be etched substantially equally during processing of the material 12 to be etched.

Abstract: Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.

Abstract: A noble metal layer is formed using ozone (O3) as a reaction gas.

Abstract: A method for manufacturing a semiconductor device using a photoresist polymer comprising a fluorine component, a photoresist composition containing the photoresist polymer and an organic solvent to reduce surface tension, by forming a photoresist film uniformly on the whole surface of an underlying layer pattern to allow a subsequent ion-implanting process to be stably performed.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device that includes: etching a semiconductor substrate to form a recess region; forming a device isolation trench in a portion of the etched semiconductor substrate including a portion of the recess region; and forming a device isolation film in the device isolation trench. The recess region is formed before the device isolation film, which can prevent a gate subsequently formed over the device isolation film from leaning. As a result, a subsequent landing plug contact hole is opened, which can improve process defects.

Abstract: A method for manufacturing a semiconductor device comprises: forming an interlayer insulating film including a storage node contact plug over a semiconductor substrate; forming an etching barrier film, a sacrificial insulating film, and a hard mask film over the storage node contact plug and the interlayer insulating film; forming a first storage node region by removing a portion of the sacrificial insulating film and the hard mask film by an etching process such that a polymer film is formed at a sidewall of the hard mask film and the sacrificial insulating film; and forming a second storage node region by removing the remaining portions of the sacrificial insulating film and the etching barrier film, thereby exposing the storage node contact plug. The method prevents a bowing phenomenon in the etching process for forming a storage node region and thus allows storage nodes having substantially vertical profiles to be formed.

Abstract: A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film.

Abstract: A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.