Abstract: A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.

Abstract: A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer.

Abstract: A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of an exposure lens and deformation of the photoresist pattern by exposure.

Abstract: An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

Abstract: In a method of forming a dual damascene pattern of a semiconductor device, horns that occur while forming a trench constituting the dual damascene pattern are removed in an intermediate process of forming the trench. Thus, the source of particles, which occur due to the horns in a cleaning process performed after the dual damascene pattern is formed, may be removed. Accordingly, an increase of contact resistance due to particles may be prevented, and a reduction in the yield of semiconductor devices may also be improved.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: A plasma etching method that can increase the selection ratio of a stop layer to an interlayer insulation film. The plasma etching method is carried out on a substrate that has the interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a stop layer that stops etching and is exposed at the bottom of a hole or a trench formed in the interlayer insulation film. The interlayer insulation film and the stop layer are exposed at the same time to plasma generated from CyFz (y and z are predetermined natural numbers) gas and hydrogen-containing gas.

Abstract: A method for fabricating a semiconductor device includes forming a device isolation structure on a semiconductor substrate to define an active region. A hard mask pattern defining a recess region is formed over the semiconductor substrate. The semiconductor substrate is selectively etched using the hard mask pattern to form a recess channel structure. The etching process for the semiconductor substrate is performed by two plasma etching methods under different etching conditions. The hard mask pattern is removed to expose the active region including the recess channel structure. A gate electrode is formed to fill the recess channel structure.

Abstract: A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set.

Abstract: A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.

Abstract: A method of wet etching semiconductor zinc tin oxide includes submerging a semiconductor zinc tin oxide film in a bath solution. The film is partially covered with a pattern of protective material, and the bath solution etches semiconductor zinc tin oxide film not covered by the protective material. A system for wet etching semiconductor zinc tin oxide includes a bath containing a bath solution. The bath solution is effective to wet etch the semiconductor zinc tin oxide.

Abstract: The present invention includes the steps of: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film to be processed; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.

Abstract: A two-step nitrogen plasma method is used for stripping a photoresist layer from over a substrate. A first step within the two-step nitrogen plasma method uses a nitrogen plasma with ion activation to form from the photoresist layer over the substrate a treated photoresist layer over the substrate. A second step within the two-step nitrogen plasma method uses a second nitrogen plasma without ion activation to remove the treated photoresist layer from over the substrate. The method is particularly useful for stripping a patterned photoresist layer that is used for forming a gate electrode from a gate electrode material layer.

Abstract: A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A second photoresist layer is formed over the BARC layer and the organic layer. An etch process is performed so that the second photoresist layer remains on the BARC layer between the first photoresist patterns and becomes a second photoresist pattern. The organic layer on the first photoresist pattern and between the first and second photoresist patterns is removed. The BARC layer formed below the organic layer is removed. The hard mask layer is etched using the first and second photoresist patterns as an etch mask. The etch target layer is etched using a hard mask pattern as an etch mask.

Abstract: A method of manufacturing a semiconductor device prevents a pattern bridge phenomenon generated by a proximity effect between patterns and a thickness lowering phenomenon of the pattern. As a result, a length of the major axis required in characteristics of the device is secured to improve an electric characteristic and an overlapping margin. A photoresist pattern is formed to have a line/space type, thereby securing a DOF margin in comparison with a photoresist pattern of an island type.

Abstract: A method for forming a pattern in a semiconductor device includes forming an etch target layer, forming a hard mask over the etch target layer, the hard mask including a multiple-layer stack structure comprising a bottom layer, a transformed layer, and an upper layer, wherein the transformed layer is formed by transforming a surface of the bottom layer. The hard mask and the etch target layer are etched.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.

Abstract: In one aspect, the invention provides a fabrication method. Before the fabrication of the structure, a mask layer, for example a hard mask, is applied to a layer. The mask layer has at least two layers composed of materials that can be etched selectively with respect to one another. In a first etching process, the structure is introduced into the layer. Subsequently, the first etching process is interrupted at a point in time in order to etch away a topmost layer of the hard mask selectively with respect to the underlying layer by means of a second etching process and, subsequently, the first etching process is continued for fabricating the structure with the new topmost layer.

Abstract: A substrate processing apparatus has a cup part for receiving processing liquid which is applied from a processing liquid applying part and is splashed from a substrate, and the cup part is formed of electrical insulation material. Hydrophilic treatment is performed on an outer annular surface of the cup part and water is held on the outer annular surface of the cup part while processing the substrate. With this structure, charged potential of the cup part generated in splashing of pure water can be suppressed by the water held on the outer annular surface, without greatly increasing the manufacturing cost of the substrate processing apparatus by forming the cup part with special conductive material. As a result, it is possible to prevent electric discharge from occurring on the substrate due to induction charging of the substrate, in application of the processing liquid onto the substrate.

Abstract: In methods of forming an opening in a semiconductor device and methods of manufacturing a semiconductor device, a mask pattern may be formed on a layer to selectively expose the layer through the mask pattern. The layer may be partially etched using the mask pattern as an etching mask and using a first etching gas including carbon under a silicon-containing gas atmosphere until a lower layer beneath the layer is exposed to form a preliminary opening. The layer may be etched using the mask pattern as an etching mask and using a second etching gas until the lower layer is exposed to form an opening through the layer. The layer may be an insulation layer.

Abstract: A method for forming an opening in a semiconductor device is provided. In one embodiment, a bottom anti-reflective coating (BARC) layer is formed overlying an insulation layer of a substrate. A patterned photoresist layer including at least one opening therein is formed overlying the BARC layer.