Chemical Or Electrical Treatment, E.g., Electrolytic Etching (epo) Patents (Class 257/E21.485)
  • Patent number: 10330941
    Abstract: A method for production of window elements which can be soldered into a housing in a hermetically tight manner with optical coating and free-form window elements are disclosed. After application of optical coatings, a protective layer is applied to the optical coating, the two layer systems are selectively removed by means of a machining beam of high-energy radiation for the purpose of ablation of a desired optically active free-form surface for window elements with any geometric shape through a localized machining beam in edge regions of the optically active free-form surface such that the protective layer remains on the optical coating as lift-off mask which is lifted off after applying a metallization for a solder layer by an etching process that acts selectively only on the protective layer but not on the optical coating, and the metallization remains only on the peripheral edge regions circumscribing the free-form surfaces.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 25, 2019
    Assignee: JENOPTIK Optical Systems GmbH
    Inventors: Elvira Gittler, Steffen Biermann, Wolfgang Brode, Falko Stoerzner
  • Patent number: 9887099
    Abstract: A method includes: forming a metal oxide film on a substrate including an etching target film and a metal pattern formed thereon, and forming an oxide film having a relatively strong oxygen bond on the metal pattern; performing a reduction treatment such that the metal oxide film formed on the metal pattern is defined as a first metal-containing film and the metal oxide film formed on the etching target film is defined as a second metal-containing film whose surface is reduced into metal; selectively forming a metal film on only the second metal-containing film formed on the etching target film, the metal film having such a property that it is easy to be formed on metal and is hard to be formed on an oxide; and obtaining an inversion pattern composed of the inversion material by etching away the metal pattern and leaving the inversion material and the metal film.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 6, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Nagai
  • Patent number: 8888952
    Abstract: Disclosed is an apparatus for wet treatment of a plate-like article, which includes: a spin chuck for holding and rotating the plate-like article including an element for holding the plate-like article at the plate-like article's edge and a gas supply element for directing gas towards the side of the plate-like article, which faces the spin chuck, wherein the gas supply element includes a gas nozzle rotating with the spin chuck, for providing a gas cushion between the plate-like article and the spin chuck; a fluid supply element for directing fluid onto the side of the plate-like article, which is facing the spin chuck, through a non-rotatable fluid nozzle.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: November 18, 2014
    Assignee: Lam Research AG
    Inventors: Markus Gigacher, Michael Brugger
  • Patent number: 8822261
    Abstract: A method of making a photovoltaic device is presented. The method includes disposing an absorber layer on a window layer. The method further includes treating at least a portion of the absorber layer with a first solution including a first metal salt to form a first component, wherein the first metal salt comprises a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The method further includes treating at least a portion of the first component with cadmium chloride to form a second component. The method further includes treating at least a portion of the second component with a second solution including a second metal salt to form an interfacial layer on the second component, wherein the second metal salt comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: September 2, 2014
    Assignee: First Solar, Inc.
    Inventors: Donald Franklin Foust, Hongbo Cao
  • Patent number: 8790953
    Abstract: The surface of silicon is textured to create black silicon on a nano-micro scale by electrochemical reduction of a silica layer on silicon in molten salts. The silica layer can be a coating, or a layer caused by the oxidation of the silicon.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 29, 2014
    Inventors: Derek John Fray, Eimutis Juzeliunas
  • Patent number: 8735188
    Abstract: An atomic layer deposition apparatus and a sealing method of an organic light emitting device using the same are disclosed. In one embodiment, the atomic layer deposition apparatus improves a structure of the purge gas injection nozzle so as to increase the exhaust efficiency of the purge gas in an atomic layer deposition process, which increases a speed of a purge process. As a result, it is possible to improve a deposition speed and a quality of a sealing film when a sealing process for sealing the organic light emitting device is implemented by using the atomic layer deposition.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Hun Kim, Sang-Joon Seo, Jin-Kwang Kim, Jun-Hyuk Cheon
  • Patent number: 8673076
    Abstract: Disclosed is a substrate processing apparatus which comprises reaction tubes (3,4) for processing multiple substrates (27), a heater (5) for heating the substrates, and gas introducing nozzles (6,7,8,9,10) for supplying a gas into the reaction tubes. Each of the gas introducing nozzles (6,7,8,9) is structured so that at least the channel cross section of a portion facing the heater (5) is larger than those of the other portions.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: March 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Naoharu Nakaiso
  • Patent number: 8633090
    Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.
    Type: Grant
    Filed: July 10, 2010
    Date of Patent: January 21, 2014
    Assignees: Shanghai Simgui Technology Co., Ltd., Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xiang Wang, Xing Wei, Miao Zhang, Chenglu Lin, Xi Wang
  • Patent number: 8610034
    Abstract: A heater for heating a wafer includes elements that are arranged at a distance from one another in a rotationally symmetrical fashion with respect to a shaft extending through a center of the wafer, an electrode being provided to each of the elements to heat the wafer uniformly.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: December 17, 2013
    Assignee: NuFlare Technology, Inc.
    Inventors: Kunihiko Suzuki, Shinichi Mitani
  • Patent number: 8501521
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a copper species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 6, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8476104
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: July 2, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8460474
    Abstract: A method of cleaning semiconductor wafers using an acid cleaner followed by an alkaline cleaner to clean contaminants from the materials is provided. The acid cleaner removes substantially all of the metal contaminants while the alkaline cleaner removes substantially all of the non-metal contaminants, such as organics and particulate material.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 11, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Robert K. Barr, Raymond Chan, Matthew L. Moynihan
  • Patent number: 8435826
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. The method forms a bulk copper indium disulfide material from a multi-layered structure comprising a copper species, an indium species, and a sulfur species overlying the first electrode layer. The bulk copper indium disulfide material comprises one or more portions of a copper poor copper indium disulfide material, a copper poor surface regions, and one or more portions of a sulfur deficient copper indium disulfide material characterized by at least a CuInS2-x species, where 0<x<2. The copper poor surface and one or more portions of the copper poor copper indium disulfide material are subjected to a sodium species derived from a sodium sulfide material to convert the copper poor surface from an n-type characteristic to a p-type characteristic.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: May 7, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8426235
    Abstract: A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: April 23, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chienliu Chang
  • Patent number: 8394662
    Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: March 12, 2013
    Assignee: Stion Corporation
    Inventor: Howard W. H. Lee
  • Patent number: 8377830
    Abstract: An electrically conductive first chemical solution is supplied to the back surface of a semiconductor substrate, on the front surface of which elements are formed. After starting supplying the first chemical solution, wet processing is performed by supplying an electrically conductive second chemical solution to the front surface of the semiconductor substrate.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Suzuki
  • Patent number: 8324112
    Abstract: A novel etching agent for etching II-VI semiconductors is provided. The etching agent includes an aqueous solution of potassium permanganate and phosphoric acid. This etching solution can etch II-VI semiconductors at a rapid rate but tend to be much less reactive with III-V semiconductors. The provided agent can be used in a method for etching II-VI semiconductors.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: December 4, 2012
    Assignee: 3M Innovative Properties Company
    Inventors: Guoping Mao, Michael W. Bench, Zai-Ming Qiu, Xiaoguang Sun
  • Publication number: 20120205045
    Abstract: A semiconductor machine and a cleaning process are provided. The semiconductor machine includes a chamber and a cleaning module. The cleaning process includes the following steps. Firstly, the semiconductor machine is used to perform a semiconductor manufacturing process, wherein a titanium-based material is etched in the semiconductor manufacturing process. Then, a cleaning task is activated to clean the semiconductor machine by using a cleaning agent including a gas mixture of a fluoride compound and oxygen.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 16, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Hsun HO, Ching-Shing Huang, Chih-Hui Shen, Tao-Min Chang
  • Publication number: 20120202355
    Abstract: A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Applicant: Spansion LLC
    Inventors: Rinji Sugino, Bradley Marc Davis, Lei Xue, Kenichi Ohtsuka
  • Publication number: 20120156885
    Abstract: In a method for processing a semiconductor wafer formed with a copper conductor, the semiconductor wafer is etched in an etching chamber to expose the copper conductor. The etched semiconductor wafer is transmitted from the etching chamber to a buffer zone, where a gas inert to the semiconductor wafer is introduced for a period of time. Then the semiconductor wafer is moved out of the buffer zone to a loading module. Nitrogen is one of the suitable options as the gas, and argon is another option.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Hsiao LEE, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 8187485
    Abstract: A diameter of a mounting unit of the stage of an ashing processing apparatus is less than a diameter of a mounting unit of the stage of an etching processing apparatus, and the diameter of the mounting unit of the stage of the etching processing apparatus is less than a diameter of an objective item.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 29, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroyuki Kobayashi, Masaru Izawa
  • Patent number: 8187963
    Abstract: A method of forming an ohmic contact to a surface of a Cd and Te containing compound film as may be found, for example in a photovoltaic cell. The method comprises forming a Te-rich layer on the surface of the Cd and Te containing compound film; depositing an interface layer on the Te-rich layer; and laying down a contact layer on the interface layer. The interface layer is composed of a metallic form of Zn and Cu.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: May 29, 2012
    Assignee: EncoreSolar, Inc.
    Inventor: Bulent M. Basol
  • Publication number: 20120115251
    Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.
    Type: Application
    Filed: January 13, 2012
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, Solomon Assefa, Eugene J. O'Sullivan
  • Publication number: 20120083130
    Abstract: Apparatus and methods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature plate within a chamber of a plasma etcher, providing a plasma source gas within the chamber, providing an anode above the feature plate and a cathode below the feature plate, connecting a portion of the cathode to the feature plate, generating plasma ions using a radio frequency power source and the plasma source gas, directing the plasma ions toward the wafer using an electric field, and providing an electrode shield around the cathode. The electrode shield is configured to protect the cathode from ions directed toward the cathode including the portion of the cathode connected to the feature plate.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: Skyworks Solutions, Inc.
    Inventors: Daniel K. Berkoh, Elena B. Woodard, Dean G. Scott
  • Patent number: 8129287
    Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Suzuki, Hidemitsu Aoki
  • Publication number: 20110318928
    Abstract: The invention provides a aqueous slurry useful for chemical mechanical polishing a semiconductor substrate having copper interconnects. The slurry comprises by weight percent, 0 to 25 oxidizing agent, 0.1 to 50 abrasive particles, 0.001 to 10 inhibitor for decreasing static etch of the copper interconnects, 0.001 to 5 poly(methyl vinyl ether) having a formula as follows: and the poly(methyl vinyl ether) is water soluble and n has a value of at least 5, 0.005 to 1 aminobutyric acid, 0.01 to 5 phosphorus-containing compound, 0 to 10 copper complexing agent formed during polishing and balance water.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Inventor: Jinru Bian
  • Publication number: 20110318936
    Abstract: A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiNy) layer overlying silicon in a plasma etching system, and transferring a pattern to the silicon nitride layer using a plasma etch process, wherein the plasma etch process utilizes a process composition having as incipient ingredients a process gas containing C, H and F, and an additive gas including CO2. The method further includes: selecting an amount of the additive gas in the plasma etch process to achieve: (1) a silicon recess formed in the silicon having a depth less than 10 nanometers (nm), and (2) a sidewall profile in the pattern having an angular deviation from 90 degrees less than 2 degrees.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akiteru KO, Christopher COLE
  • Publication number: 20110306213
    Abstract: A quartz window with an interior plenum is operable as a shutter or UV filter in a degas chamber by supplying the plenum with an ozone-containing gas. Pressure in the plenum can be adjusted to block UV light transmission into the degas chamber or adjust transmittance of UV light through the window. When the plenum is evacuated, the plenum allows maximum transmission of UV light into the degas chamber.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 15, 2011
    Applicant: Lam Research Corporation
    Inventors: Yen-Kun Victor Wang, Shang-I Chou, Jason Augustino
  • Patent number: 8076250
    Abstract: A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: December 13, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Ji Ae Park, Tsutomu Kiyohara, Sohyun Park, Bok Hoen Kim
  • Publication number: 20110300714
    Abstract: An assembly comprises a component of a plasma process chamber, a thermal source and a polymer composite therebetween exhibiting a phase transition between a high-thermal conductivity phase and a low-thermal conductivity phase. The temperature-induced phase change polymer can be used to maintain the temperature of the component at a high or low temperature during multi-step plasma etching processes.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Applicant: Lam Research Corporation
    Inventors: Tom Stevenson, Michael Dickens
  • Publication number: 20110275216
    Abstract: A chemical mechanical polishing method includes employing a topologically selective slurry or an abrasive trapped or abrasive mounted pad in an initial polishing operation to provide a substantially planar topology of a polysilicon layer of a semiconductor wafer, and performing a second polishing operation to remove a portion of the polysilicon layer to expose discrete elements of the semiconductor wafer.
    Type: Application
    Filed: May 4, 2010
    Publication date: November 10, 2011
    Inventors: Chun Fu Chen, Yung Tai Hung, Chin-Ta Su, Ta-Hung Yang
  • Publication number: 20110266537
    Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Yan Ye
  • Publication number: 20110263129
    Abstract: Disclosed is a method of etching semiconductor nanocrystals, which includes dissolving semiconductor nanocrystals in a halogenated solvent containing phosphine so that anisotropic etching of the surface of semiconductor nanocrystals is induced or adding a primary amine to a halogenated solvent containing phosphine and photoexciting semiconductor nanocrystals thus inducing isotropic etching of the surface of the nanocrystals, thereby reproducibly controlling properties of semiconductor nanocrystals including absorption wavelength, emission wavelength, emission intensity, average size, size distribution, shape, and surface state.
    Type: Application
    Filed: December 28, 2010
    Publication date: October 27, 2011
    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Seung Koo Shin, Won Jung Kim, Sung Jun Lim
  • Publication number: 20110253313
    Abstract: The present invention provides a plasma processing apparatus in which a plasma distribution, a plasma potential, an etching characteristic or a surface processing characteristic varies in time and spatially, and controllability and reliability are high. In the plasma processing apparatus, at least part of a discharge forming electromagnetic wave is introduced into a processing chamber through a transmission electrode. The transmission electrode is provided with a transmission electrode layer as at least part of constituent elements therefor. Slender-shaped slot opening areas are densely formed in the transmission electrode layer. The transmission electrode behaves like a material having electrical conductivity for an RF bias electromagnetic wave or ion plasma vibrations, thereby implementing high stability and high reliability of plasma characteristics and plasma processing characteristics.
    Type: Application
    Filed: August 12, 2010
    Publication date: October 20, 2011
    Inventors: Keizo SUZUKI, Ken Takei, Takehito Usui, Masami Kamibayashi, Nobuyuki Negishi
  • Publication number: 20110249938
    Abstract: An apparatus includes a crystalline inorganic semiconductor substrate. A planar optical waveguide core is located over the substrate such that a first length of the planar optical waveguide core is directly on the substrate. A regular array of optical scattering structures is located within a second length of the planar optical waveguide core. A cavity is located in the substrate between the regular array and the substrate.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 13, 2011
    Applicant: Alcatel-Lucent USA, Incorporated
    Inventors: Long Chen, Liming Zhang, Christopher Doerr, Nicolas Dupuis
  • Publication number: 20110244683
    Abstract: A semiconductor structure is fabricated with a void such as a line, contact, via or zia. To prevent slurry particles from falling into and remaining in a void during a chemical-mechanical planarization process, a protective coat is provided in the void to trap the slurry particles and limit an extent to which they can enter the void. A metal layer is provided above the protective coat. Subsequently, the protective coat and trapped slurry particles are removed by cleaning, leaving a void which is substantially free of slurry particles. This is beneficial such as when the void is used as an alignment mark. The protective coat can be an organic layer such as spin-on carbon or i-line photoresist, an ashable material such as amorphous carbon, or a dissolvable and selective material such as SiN.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 6, 2011
    Inventor: Michiaki Sano
  • Publication number: 20110232843
    Abstract: A seal for sealing an interface between a container and a lid of a process chamber. The seal comprises a first seal element and a second seal element that are arranged to seal the interface in series, with the second seal element being situated to encounter processing activity upstream of the fist seal element. The first seal element has a deflectable portion and a protrusion extending radially from the deflectable portion. The second seal element has a radially extending recess in which the protrusion of the first seal element is received. The protrusion and recess interlock to restrict separation and/or rotation of the first and second seal elements. Inclined surfaces of the first seal element interact with the second seal element to apply axial sealing forces to sealing surfaces of the second seal member.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Inventors: Don Bowman, Stephen Coppola, Kenneth W. Cornett, Dan Funke, Julian Kamibayashiyama, Jeff Navarro, Jeremy M. Payne, Donald J. Peterson, Douglas C. Schenk
  • Publication number: 20110217806
    Abstract: An electrode (3i) of a radiofrequency parallel plate plasma reactor comprises an electrode surface of a multitude of surfaces of metal members (28) which reside on dielectric spacing members (29), whereby the metal members (28) are mounted in an electrically floating manner. The dielectric members (29) are mounted, opposite to the metal members (28), upon a metal Rf supply body (14a).
    Type: Application
    Filed: September 28, 2009
    Publication date: September 8, 2011
    Applicant: OERLIKON SOLAR AG, TRUEBBACH
    Inventor: Stephan Jost
  • Patent number: 8012772
    Abstract: A substrate treating apparatus, in which a voltage is applied to between a treatment electrode and a target substrate in such a state that the treatment electrode is opposed to the target substrate to thereby perform substrate treatment for removing undesired substances on the target substrate, has a reference electrode, a transfer unit which transfers at least one of the treatment electrode and the reference electrode to thereby provide the treatment electrode so that the treatment electrode is opposed to the reference electrode, and a check unit for applying a voltage to between the treatment electrode and the reference electrode in such a state that the treatment electrode is opposed to the reference electrode and thereby checking an adhesion level of undesired substances onto the treatment electrode surface.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: September 6, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Koide, Yasushi Iseki, Akira Ishii
  • Publication number: 20110207332
    Abstract: A plasma processing apparatus used in semiconductor device manufacturing includes a process kit formed of insulating materials such as quartz and coated with a Y2O3 coating. The Y2O3 coating is a thin film formed using suitable CVD or PVD operations. The Y2O3 coating is resistant to degradation in fluorine etching chemistries commonly used to etch silicon in semiconductor manufacturing. The plasma processing apparatus may be used in etching, stripping and cleaning operations. Also provided in another embodiment is a plasma processing apparatus having a quartz process kit coated with a sapphire-like film.
    Type: Application
    Filed: May 12, 2010
    Publication date: August 25, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Shui LIU, Yeh-Chieh WANG, Jiun-Rong PAI
  • Publication number: 20110207245
    Abstract: A stage onto which is electrostatically attracted a substrate to be processed in a substrate processing apparatus, which enables the semiconductor device yield to be improved. A temperature measuring apparatus 200 measures a temperature of the substrate to be processed. A temperature control unit 400 carries out temperature adjustment on the substrate to be processed such as to become equal to a target temperature based on a preset parameter. A temperature control unit 400 controls the temperature of the substrate to be processed by controlling the temperature adjustment by the temperature control unit 400 based on a measured temperature measured by the temperature measuring apparatus 200.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Chishio KOSHIMIZU, Tomohiro Suzuki
  • Publication number: 20110195575
    Abstract: The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 11, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shiang-Bau WANG
  • Publication number: 20110186228
    Abstract: A showerhead is disclosed in this invention. The showerhead includes a bottom portion, at least one plate, and a top portion. The bottom portion includes a plurality of gas tubes which are integratedly formed on the bottom portion. The gas tubes include at least one first gas tube. The at least one plate includes a first plate. The first plate includes a plurality of first openings, wherein the gas tubes pass through the first openings. The top portion is coupled to the bottom portion for forming at least one inner space.
    Type: Application
    Filed: April 9, 2010
    Publication date: August 4, 2011
    Applicant: HERMES-EPITEK CORPORATION
    Inventors: Chien-Ping Huang, Tsan-Hua Huang
  • Patent number: 7985982
    Abstract: An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a method of manufacturing a flat panel display using the etchant. The etchant includes nitric acid, phosphoric acid, acetic acid, and an acetate compound in addition to water.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Kyun Kim, Hong-Sick Park, Jong-Hyun Choung, Sun-Young Hong, Ji-Sun Lee, Byeong-Jin Lee, Kui-Jong Baek, Tai-Hyung Rhee, Yong-Sung Song
  • Publication number: 20110177692
    Abstract: This invention relates to a method and apparatus by integrating semiconductor manufacturing processes of stress free electrochemical copper polishing (SFP), removal of the Tantalum oxide or Titanium oxide formed during SFP process and XeF2 gas phase etching barrier layer Ta/TaN or Ti/TiN process. Firstly, at least portion of plated copper film is polished by SFP. Secondly the barrier metal oxide film formed during SFP process is etched away by etchant. Finally, the barrier layer Ta/TaN or Ta/TiN is removed with XeF2 gas phase etching. The apparatus accordingly consists of three sub systems: stress free copper electropolishing system, barrier layer oxide film removal system and barrier layer Ta/TaN or Ti/TiN gas phase etching system.
    Type: Application
    Filed: August 20, 2008
    Publication date: July 21, 2011
    Inventors: Jian Wang, Zhaowei Jia, Junping Wu, Liangzhi Xie, Hui Wang
  • Publication number: 20110165779
    Abstract: Methods for orienting an upper electrode relative to a lower electrode are provided. The lower electrode is configured to have a desired existing orientation in a process chamber to define active and inactive process zones in the process chamber for processing a wafer. The method includes configuring each electrode with a reference surface, where a lower electrode reference surface is in the desired existing orientation and an upper electrode reference surface to be oriented parallel to the lower electrode reference surface. Then, temporarily holding the upper electrode reference surface oriented parallel to the lower electrode reference surface, and securing the upper electrode to a drive to mount the upper electrode reference surface parallel to the lower electrode reference surface. Other method configurations are also disclosed and illustrated.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Alan M. Schoepp, John D. Boniface
  • Publication number: 20110151675
    Abstract: A spin chuck in an apparatus for single wafer wet processing has structures at its periphery that, in combination with a supported wafer, form a series of annular nozzles that direct flowing gas from a chuck-facing surface of the wafer, around the edge of the wafer, and exhaust the gas away from the non-chuck-facing surface of the wafer, thereby preventing treatment fluid applied to the non-chuck-facing surface from contacting the edge region of the wafer. Retaining pins with enlarged heads engage the wafer edge and prevent it from being displaced upwardly when a high flow rate of gas is utilized.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Applicant: LAM RESEARCH AG
    Inventors: Dieter FRANK, Michael PUGGL
  • Publication number: 20110143546
    Abstract: An ashing device and ashing method that can positively remove resist from a wafer while preventing degradation of the film material properties of exposed porous Low-K film on the wafer. The ashing device of the present invention introduces a gas to a dielectric plasma generating chamber 14, excites said gas to generate a plasma, and performs plasma processing using said gas plasma on a processing work S in use of a Low-K film. The ashing gas introduced from a gas regulator 20 is an inert gas to which H2 has been added. The configuration is formed so that plasma is generated from the gas blend, and the resist is removed by the hydrogen radicals generated.
    Type: Application
    Filed: February 21, 2011
    Publication date: June 16, 2011
    Inventor: Katsuhiro Yamazaki
  • Publication number: 20110132541
    Abstract: A wafer stage includes a first evaporator where a refrigerant circulates. The first evaporator makes up a cooling cycle with a compressor, first condenser, expansion valve, second evaporator, refrigerant thermometer, and refrigerant flowmeter. The first condenser is supplied with a heat exchange medium. The temperature of a coolant supplied to the second evaporator is measured by an inlet refrigerant thermometer and outlet refrigerant thermometer, while the flow rate of the coolant is monitored and adjusted by a flow-rate adjuster. The temperature difference in the coolant between being at the inlet and at the outlet and flow rate can be measured. Upon complete evaporation of the refrigerant in the second evaporator, the dryness of the refrigerant discharged from the wafer stage is calculated from the amount of heat absorbed from (exchanged with) the coolant, the circulation amount of the refrigerant and the refrigerant temperature to control the rotational speed of the compressor.
    Type: Application
    Filed: January 29, 2010
    Publication date: June 9, 2011
    Inventors: Takumi TANDOU, Masaru Izawa
  • Publication number: 20110124144
    Abstract: A substrate processing apparatus includes an evacuatable process chamber configured to receive a substrate carrier having at least one substrate, a plasma generating module, a gas feed, a gas discharge and a vapor etching module provided in the process chamber. A substrate processing method includes introducing a substrate carrier including at least one substrate into an evacuatable process chamber, generating a plasma in a plasma process using a plasma generating module in a gas or a gas mixture, performing a vapor etching of the at least one substrate before, after or alternatingly with the plasma process and performing at least one of a coating, etching, surface modification and cleaning of the substrate.
    Type: Application
    Filed: March 17, 2009
    Publication date: May 26, 2011
    Applicant: ROTH & RAU AG
    Inventors: Hermann Schlemm, Matthias Uhlig