Abstract: According to one embodiment, a semiconductor memory includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion.

Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.

Abstract: A module assembly device (402) is configured for assembling a module assembly (114) for a detector array (110) of an imaging system (100). The module assembly device includes a base (400) having a long axis (401). The module assembly device further includes a first surface (406) of the base and side walls (408) protruding perpendicular up from the first surface and extending in a direction of the long axis along at least two sides of the base. The first surface and side walls form a recess (404) configured to receive the module substrate on the surface and within the side walls. The module assembly device further includes protrusions (403) protruding from the side walls in a direction of the side walls. The protrusions and side walls interface forming a ledge which serves as a photo-detector array tile support (410) configured to receive the photo-detector array tile (118) over the ASIC and the module substrate.

Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.

Abstract: An electronics composition includes a curable matrix material and, optionally, a filler material disposed within the matrix material. The cured matrix material includes an oligomer or polymer material derived from a compound selected from a methylene malonate monomer, a multifunctional methylene monomer, a methylene beta ketoester monomer, a methylene beta diketone monomer, or a mixture thereof.

Abstract: Devices and techniques are disclosed herein which include a first LED device layer, a second LED device layer, and an adhesive bondline disposed between the first LED device layer and the second LED device layer. The adhesive bondline includes a bondline thickness, a plurality of spacers disposed within the adhesive bondline, and a silicone matrix. The plurality of spacers may have a diameter or a shortest axis between 0.5 and 10 micrometers and the coefficient of variation is 10% or less. The plurality of spacers may be include SiO2, alumina, soda lime glass, may be inorganic, or polymeric.

Abstract: Provided is a metal powder sintering paste having a high resistance to thermal stress. The present invention provides a metal powder sintering paste containing silver particles having an average particle diameter (median diameter) of 0.3 ?m to 5 ?m as a main component, further containing inorganic spacer particles having a CV value (standard deviation/average value) of less than 5%, and containing substantially no resin.

Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.

Abstract: In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.

Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.

Abstract: A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a surface of a printed wiring board. The surface of the package substrate and the surface of the printed wiring board face each other. The plurality of lands and another plurality of lands are bonded to each other with solder having a height of 30% or less of a diameter of a solder bonding portion at the corresponding land. A ratio of a solder bonded area of at least each of lands, among another plurality of the lands, of which distance value to a corresponding one of the lands is larger than an average distance value between the lands and another lands, to a solder bonded area of the corresponding one of the lands is 56% or more and 81% or less.

Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.

Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.

Abstract: A light-emitting device includes a light-emitting element, a light pervious layer, an electrode defining layer, a first soldering pad and a second soldering pad. The light-emitting element has an upper surface, a bottom surface, and a lateral surface arranged between the upper surface and the bottom surface. The light pervious layer covers the upper surface and the lateral surface. The electrode defining layer covers a part of the light pervious layer. The first soldering pad and the second soldering pad are surrounded by the electrode defining layer. A gap is located between the first soldering pad and the second soldering pad while the gap remains substantially constant.

Abstract: The present invention provides a novel cyanate ester compound which has excellent solvent solubility and from which a hardened product having a low coefficiency of thermal expansion and excellent flame retardancy and heat resistance is obtained. The present invention is a cyanate ester compound obtained by cyanating a naphthol-dihydroxynaphthalene aralkyl resin or a dihydroxynaphthalene aralkyl resin.

Abstract: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Abstract: A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material.

Abstract: A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate; mounting at least a first electronic component on the substrate; positioning a handle wafer above the first electronic component; attaching the first electronic component to the substrate via electrical connectors between the first electronic component and the substrate; and while attaching the first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the first electronic component, to manage planarity of the first electronic component during the attaching. In an embodiment, a joining process is used to attach the first electronic component to the substrate via the electrical connectors. For example, thermal compression bonding may be used to attach the first electronic component to the substrate via the electrical connectors.

Abstract: A semiconductor device includes a semiconductor element, a laminated substrate including an insulating board and a circuit board disposed on the insulating board, the semiconductor element being mounted on the circuit board, a surrounding case having an opening, and being disposed on the outer peripheral portion of the insulating board to surround the circuit board, a relay substrate having a through hole and being disposed on the surrounding case to cover the opening, and an external connection terminal including a first end portion bonded to the circuit board, a second end portion, opposite to the first end portion, inserted into the through hole of the relay substrate from the rear surface of the relay substrate so as to be in contact with the front surface of the relay substrate, and an elastically deformable elastic portion between the first end portion and the second end portion.

Abstract: Various embodiments of the present disclosure include a non-volatile memory semiconductor device and a device that uses the same, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present disclosure, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.

Abstract: A method for estimating stress of an electronic component. An electronic component including first and second elements and conductive bumps is provided. Each conductive bump has two surfaces connected to the first and second elements respectively. Two adjacent conductive bumps have a pitch therebetween. The conductive bumps includes a first conductive bump and second conductive bumps. A stress value of the first conductive bump related to a testing parameter is calculated. A stress value of each second conductive bump related to the testing parameter is calculated according to a first calculating formula. The first calculating formula is ? 2 = L D - 2 ? r ? ? 1 , ?2 is the stress of each second conductive bump, L is a beeline distance between each second conductive bump and the first conductive bump, D is an average value of the pitches of the conductive bumps, r is a radius of each surface, and ?1 is the stress value of the first conductive bump.

Abstract: A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.

Abstract: In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die.

Abstract: A detachable probe card interface comprises a space transformer, a deformable connector, and a carrier board. The space transformer includes first electrical contacts and second electrical contacts, wherein the first electrical contacts are coupled to the second electrical contacts through one or more layers of the space transformer. The deformable connector includes a plurality of conductive particles arranged in columns coinciding with the second electrical contacts, wherein the conductive particles compress with one another when one or more forces are exerted on the deformable connector. The carrier board includes a plurality of vias aligned with the plurality of second electrical contacts on the space transformer, and a plurality of conductors disposed within the vias.

Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Abstract: A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.

Abstract: Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

Abstract: Methods of forming near field transducers (NFTs) including electrodepositing a plasmonic material.

Abstract: The subject matter of this specification generally relates to electronic packages. In some implementations, a lidless electronic package includes a substrate having a surface and a die disposed on the surface of the substrate. The die has an outside perimeter, a bottom surface adjacent to the surface of the substrate, and a top surface. The electronic package includes a stiffener disposed on the surface of the substrate. The stiffener includes a first surface that is a first distance from the surface of the substrate and a second surface disposed between the die and the first surface. The first distance is greater than a distance between the surface of the substrate and the top surface of the die. The second surface is a second distance from the surface of the substrate that is less than the distance between the surface of the substrate and the top surface of the die.

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

Abstract: A first semiconductor package of a POP structure has a first body and a plurality of first solder balls. A second semiconductor package of the POP structure has a second body and a plurality of second solder balls. A stand-off mechanism is utilized to maintain a minimum gap between the first body and the second body while a reflow soldering process is performed. By performing the reflow soldering process, the first solder balls and the second solder balls are heated and engaging with one another so as to solder the first solder balls and the second solder balls to form a plurality of interposer solder balls. Each interposer solder ball has a height substantially equal to the minimum gap and a cross sectional width less than a pitch between two adjacent interposer solder balls. Thereby, the POP structure would be a fine pitch package.

Abstract: Indentation visibility is improved and quick and accurate inspection is performed after a connection step using an anisotropic conductive film. A connection body according to the present disclosure comprises a transparent substrate and an electronic component connected to the transparent substrate via an anisotropic conductive adhesive; conductive particles contained by the anisotropic conductive adhesive cause a plurality of indentations arranged in an in-plane direction of a terminal of the transparent substrate.

Abstract: A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a surface of a printed wiring board. The surface of the package substrate and the surface of the printed wiring board face each other. The plurality of lands and another plurality of lands are bonded to each other with solder having a height of 30% or less of a diameter of a solder bonding portion at the corresponding land. A ratio of a solder bonded area of at least each of lands, among another plurality of the lands, of which distance value to a corresponding one of the lands is larger than an average distance value between the lands and another lands, to a solder bonded area of the corresponding one of the lands is 56% or more and 81% or less.

Abstract: An electronic component includes an electronic element including outer electrodes on a surface, a substrate terminal on which the electronic element is mounted, and a conductor that covers at least a portion of the substrate terminal. The substrate terminal includes a first main surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface. The substrate terminal includes a mounting electrode that is provided on the first main surface and is electrically connected to the outer electrodes of the electronic element. The mounting electrode includes adjacent portions that are located to be adjacent to the side surface of the substrate terminal. The conductor covers at least a portion of the adjacent portion.

Abstract: A method of making a device having a component with a planar surface bonded to a supporting frame with openings therein by an adhesive layer cured by actinic rays, wherein part of the adhesive layer lies in the shadow of opaque portions of the supporting frame, involves bringing the component and supporting frame together with a layer of adhesive applied between them. The part of the adhesive layer in the shadow of the opaque portions is cured by directing actinic rays obliquely through the openings so that they are reflected internally into the part of the adhesive layer in the shadow of the opaque portions.

Abstract: A method of manufacturing a semiconductor package includes preparing a package substrate including a semiconductor chip mounting region. A semiconductor chip is mounted in the semiconductor chip mounting region. A dam surrounding the semiconductor chip is formed. The formation of the dam includes depositing a first solution having a temperature below a set first temperature. A region under the semiconductor chip and a region defined by the dam are filled with an underfill by depositing the first solution having a temperature equal to or higher than the set first temperature.

Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.

Abstract: Provided is a method of fabricating a semiconductor package. The method includes providing a package substrate including a pad, mounting a semiconductor chip with a solder ball on the package substrate to allow the solder ball to be disposed on the pad, filling a space between the package substrate and the semiconductor chip with a underfill resin including a reducing agent comprising a carboxyl group, and irradiating the semiconductor chip with a laser to bond the solder ball to the pad, wherein the bonding of the solder ball to the pad comprises changing a metal oxide layer formed on surfaces of the pad and the solder ball to a metal layer by heat generated by the laser.

Abstract: The invention relates to a cased electrical component comprising a carrier substrate (10), a spring device (20), which is arranged on the carrier substrate (10), a chip (30), which on a first side (31) of the chip is coupled to the spring device (20), and a cover element (100), which is arranged on the carrier substrate (10). The cover element (100) is arranged over the chip (20) such that the cover element (100) is in contact with the chip (30) at least on a second side (32) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.

Abstract: This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.

Abstract: A probe guide plate used for a semiconductor inspection apparatus that inputs and outputs an electrical signal for inspecting an object via a probe needle, the probe guide plate includes a silicon substrate provided with a through hole that penetrates the silicon substrate from one surface to another surface through which the probe needle is inserted, the through hole including a first tapered portion provided at an end portion at the one surface side such that the hole size of which increases as it approaches the one surface, and a second tapered portion provided at an end portion at the other surface side such that the hole size of which increases as it approaches the other surface; and a silicon oxide film formed on an inner wall surface of the through hole including the first tapered portion and the second tapered portion.

Abstract: Techniques for providing a unified underfill and encapsulation for integrated circuit die assemblies. These techniques include a molding technique that includes dipping a die assembly including a substrate and one or more dies into a chamber having molding material, sealing the chamber, and lowering pressure in the chamber to coax the molding material into space between the die(s) and substrate. The use of this molding technique, as contrasted with a capillary underfill technique in which underfill material is laid down adjacent dies and fills space under the die via capillary action, provides several benefits. One benefit is that the molding material can include a higher silica particle filler content (% by weight) than the material for the capillary underfill technique, which improves CTE. Another benefit is that various design constraints related to, for example, warpage and partial underfill are eliminated or improved.

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Abstract: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.