Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.

Abstract: A material sheet is provided having antenna patterns that include first and second coupling portions that are transported toward a mounting position, and an adhesive member that is disposed on the material sheet before reaching the mounting position. At a pickup position, a mounting device picks up an RFIC module including an RFIC chip and first and second terminal electrodes connected to the RFIC chip. At the mounting position, the mounting device mounts the picked-up RFIC module onto the adhesive member on the material sheet so that the first coupling portion and the first terminal electrode face each other and so that the second coupling portion and the second terminal electrode face each other.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (?m) to about 30 ?m.

Abstract: A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.

Abstract: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; a bottom interior layer enclosed by the bottom exterior layer; and a cavity enclosed by the bottom interior layer.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the to package structure; and a cavity enclosed by the bottom exterior layer.

Abstract: A processing method of a workpiece includes an integration step of heating and compression bonding a thermocompression bonding sheet to an annular frame that has an opening to receive the workpiece therein and to the workpiece received in the opening, whereby the annular frame and the workpiece are integrated via the thermocompression bonding sheet, and a processing step of processing the workpiece integrated with the annular frame via the thermocompression bonding sheet. In the integration step, the thermocompression bonding sheet is pressed against the annular frame that has been heated by a heat table with a heat source included therein, by a heat roller with a heat source included therein while being heated by the heat roller, whereby the thermocompression bonding sheet is fixed to the annular frame.

Abstract: A method of operating a wire bonding machine is provided. The method includes: (a) operating a wire bonding machine during at least one of (i) an automatic wire bonding operation and (ii) a dry cycle wire bonding operation, wherein a bonding force is applied during the operation of the wire bonding machine; and (b) monitoring an accuracy of the bonding force of the wire bonding machine during the at least one of (i) an automatic wire bonding operation and (ii) a dry cycle wire bonding operation.

Abstract: A semiconductor package structure and a method of manufacturing the semiconductor package structure are disclosed. The semiconductor package structure includes a first semiconductor device having an active surface, a redistribution structure in electrical connection with the first semiconductor device, and a second semiconductor device bonded to the active surface of the first semiconductor device, and disposed between the first semiconductor device and the redistribution structure.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Abstract: A semiconductor package includes a lower semiconductor chip having a lower semiconductor substrate and upper pads on a top surface of the lower semiconductor substrate, an upper semiconductor chip stacked on the lower semiconductor chip, the upper semiconductor chip including an upper semiconductor substrate and solder bumps on a bottom surface of the upper semiconductor substrate, and a curing layer between the lower semiconductor chip and the upper semiconductor chip, the curing layer including a first curing layer adjacent to the upper semiconductor chip, the first curing layer including a first photo-curing agent, and a second curing layer between the first curing layer and the top surface of the lower semiconductor substrate, the second curing layer including a first thermo-curing agent.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature.

Abstract: A display device includes a display substrate including a plurality of first pads arranged in a first pad area and a plurality of second pads arranged in a second pad area, wherein the first pads and the second pads are arranged in different rows from each other, a circuit board including first circuit pads facing the first pads, respectively, and second circuit pads facing the second pads, respectively, and an adhesive member disposed between the display substrate and the circuit board and including an adhesive layer and a plurality of conductive balls distributed in the adhesive layer. Here, a first density of first conductive balls overlapping the first pad area among the conductive balls is greater that a second density of second conductive balls overlapping the second pad area among the conductive balls.

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

Abstract: Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar.

Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

Abstract: A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

Abstract: An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.

Abstract: Various system embodiments for millimeter-wave chip packaging are disclosed in the present disclosure for smooth millimeter wave signal transition and good multi-channel signal isolation. The chip packaging features a substrate and a chip electrically connected using a plurality of metal pillars. A signal pillar and surrounding metal pillar may form a ground-signal-ground (GSG) pillar structure. A chip coplanar waveguide (CPW) structure may be formed on the chip around a signal path. A substrate CPW structure may also be form around a signal strip, which is electrically connected to the signal path. Characteristic impedances of the GSG pillar structure, the chip CPW structure and the substrate CPW structure may be within a predetermined range of each other to ensure smooth millimeter wave signal transition with minimum signal loss or distortion.

Abstract: In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.

Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.

Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.

Abstract: Semiconductor devices including continuous-core connectors and associated systems and methods are disclosed herein. The continuous-core connectors each include a peripheral wall that surrounds an inner-core configured to provide an electrical path using uniform material.

Abstract: A semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed over the first semiconductor chip; and a bump structure interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core portion and a shell portion, the shell portion surrounding all side ails of the core portion, and wherein the shell portion has a higher melting point than the core portion.

Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.

Abstract: An apparatus having a seal plate which includes rigid hard portions and one or more flexible soft portions located between the hard portions is used for bonding at least one semiconductor device onto a substrate that is supported on a platform. The seal plate is movable between a first position which is spaced from the substrate and a second position whereat a first side of the seal plate is configured to be in contact with the substrate. A diaphragm covers a second side of the seal plate opposite to the first side. A fluid pressure generator exerts a fluid pressure onto the diaphragm to actuate the diaphragm to compress the one or more soft portions to transmit a bonding force onto the at least one semiconductor device during bonding.

Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.

Abstract: A semiconductor manufacturing apparatus includes; a component separating apparatus configured to separate a defective component from a substrate, a bump conditioning apparatus including an end mill cutter and receiving the substrate following separation of the defective component from the substrate, the bump conditioning apparatus being configured to cut a first connection bump using the end mill cutter to provide a conditioned first connection bump, and the first connection bump being exposed by separating the defective component from the substrate, and a component attaching apparatus configured to receive the substrate following provision of the conditioned first connection bump, and mount a new component including a second connection bump to the substrate by coupling the second connection bump and the conditioned first connection bump.

Abstract: An electrode-equipped passive component is an electrode-equipped passive component to be mounted on a mount target, and includes a passive component main body, an electrode provided on a mount surface of the passive component main body, and an underfill layer provided on the mount surface of the passive component main body. The underfill layer includes a thermosetting resin, a flux, and a solvent, and has a surface having a skin layer. The skin layer has tack power equal to or smaller than 25 mN/mm2 at room temperature and equal to or larger than 60 mN/mm2 at 40° C.

Abstract: Provided is a semiconductor package including a first bump pad on a first substrate, a second bump pad on a second substrate, a core material for reverse reflow between the first bump pad and the second bump pad, and a solder member forming a solder layer on the core material for reverse reflow. The solder member is in contact with the first bump pad and the second bump pad. Each of a first diameter of the first bump pad and a second diameter of the second bump pad is at least about 1.1 times greater than a third diameter of the core material for reverse reflow. The core material for reverse reflow includes a core, a first metal layer directly coated on the core, and a second metal layer directly coated on the first metal layer.

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: This document describes systems and techniques of a depth-adaptive mechanism for ball grid array dipping. In an aspect, a depth-adaptive mechanism having a tensioned mesh is positioned in a reservoir filled with flux. When solder balls of an integrated circuit component are dipped into the reservoir of flux, the solder balls are pressed up against the tensioned mesh. The tensioned mesh is configured to, first, elastically deform under the downward force applied by the solder balls and, second, provide an equal and opposite pushing force in order to facilitate solder ball extraction. In so doing, the solder balls of an integrated circuit component can be more easily extracted from flux when deep ball grid array dipping is performed.

Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

Abstract: An anisotropic conductive film (ACF) structure and a hot-pressing method and a hot-pressing assembly thereof are provided. The ACF structure includes an ACF and a copper/gold foil surface layer as a substrate. The ACF structure is hot-pressed by a hot-pressing method, which includes the following steps: allowing, when the ACF is in a molten state, the copper/gold foil surface layer and a bonded part to be conductive respectively to generate a magnetic field around to enhance the attraction of the copper/gold foil surface layer and the bonded part to conductive particles inside the ACF; and applying, when the ACF is in a curing stage, a closed circuit to ends of the copper/gold foil surface layer and the bonded part to perform real-time detection on the ACF to ensure the effectiveness of the hot pressing.

Abstract: According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, and a plurality of underfills between the package substrate and the semiconductor chip. The package substrate includes a trench formed in the package substrate and a plurality of dams on both sides of the trench, respectively. The top surfaces of the plurality of dams may be positioned at a lower level than the bottom surface of the semiconductor chip in a cross-sectional view of the semiconductor package with the package substrate providing a base reference level.

Abstract: This application discloses a circuit board and a manufacturing method of the circuit board. The circuit board includes a signal transmission pin pad configured to connect with signal transmission pins of an external same kind connectors to transmit a signal, and fixing pads configured to fix fixing pins of the connectors. A number, location, and size of the fixing pads are matched with a same kind connector. The same kind connector is a connector with a same number of signal transmission pins and a same distance of pins. The number of the fixing pads is greater than or equal to a maximum number of fixing pins of the same kind connector.

Abstract: Improved RFID devices and manufacturing methods that utilize more efficient RFID designs, result in less manufacturing material waste and increased recycling opportunities, all without sacrificing RFID device performance, are disclosed herein. Some exemplary embodiments of the improved RFID device may make use of a thinner foil, a hollowed-out foil, a “no-strip” design, or a tessellated design that may reduce material usage. Other exemplary embodiments may use a lower-impact and/or biodegradable adhesive so as to improve aluminum recycling and lessen risks to the environment.

Abstract: A method of making a micro-module structure comprises providing a substrate, the substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post, the component having a component top side and a component bottom side opposite the component top side, the component bottom side disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

Abstract: A picking apparatus is configured to pick up a plurality of micro elements. The picking apparatus includes an elastic plate, a substrate, a temperature-controlled adhesive layer, at least one heating element and a power source. The elastic plate has a first surface and a second surface opposite to each other. The substrate is disposed on the first surface. The temperature-controlled adhesive layer is disposed on the second surface and configured to adhere the micro elements. The heating element is disposed between the second surface and the temperature-controlled adhesive layer. The power source is electrically connected with the heating element. A viscosity of the temperature-controlled adhesive layer varies with a temperature of the temperature-controlled adhesive layer.

Abstract: Disclosed are a method of uniformly dispersing nickel-plated conductive particles of a single layer within a polymer film by applying a magnetic field to the polymer film and a method of fabricating an anisotropic conductive film using the same. The method of fabricating a film may include forming a liquefied polymer layer by roll-to-roll coating a polymer solution in which a plurality of conductive particles has been mixed, dispersing the plurality of conductive particles included in the liquefied polymer layer by applying a magnetic field to the liquefied polymer layer, and fabricating a solid polymer layer limiting a movement of the plurality of dispersed conductive particles by drying the liquefied polymer layer in which the plurality of conductive particles has been dispersed.

Abstract: An embedded component structure includes a circuit board, a chip, and a heat dissipation element. The chip is embedded in the circuit board. The heat dissipation element surrounds the chip. The chip, the circuit board, and the heat dissipation element are electrically connected. The heat dissipation element includes a first part, a second part, and a third part located between the first part and the second part. The first part is in direct contact with a side wall of the chip. The second part is a ground terminal. A method for manufacturing an embedded component structure is also provided.

Abstract: A mobile Internet-of-Things (IoT) edge device, comprising a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array (FPGA) die element and a reconfigurable die element capable of serving as storage memory or as configuration memory based on configuration information; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit and including an antenna; a radio-frequency chip (RFIC) coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; circuitry configured to translate the incoming signals to incoming data or transmit the outgoing data to outgoing signals; and a system interface configured to transmit the incoming data to the reconfigurable processor unit for processing, and configured to receive the outgoing data from the reconfigurable p