Mounting On Insulating Member Provided With Metallic Leads, E.g., Flip-chip Mounting, Conductive Die Mounting (epo) Patents (Class 257/E21.511)
  • Patent number: 10340063
    Abstract: A chip resistor includes a resistive element, first and second electrodes disposed on a lower surface the resistive element, a protective film disposed on the lower surface of the resistive element and between the first and second electrodes. The resistive element has first and second recesses therein. The first recess extends from the lower surface along a first edge surface and does not reach an upper surface of the resistive element. The second recess extends from the lower surface along a second edge surface and does not reach the upper surface of the resistive element. The first and second electrodes are disposed between the first and second recesses. The protective film is disposed between the first and second electrodes. A first plating layer disposed on the first electrode and an inner surface of the first recess. A second plating layer is disposed on the second electrode and an inner surface of the second recess. This chip resistor avoids mounting failures.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 2, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuharu Kinoshita, Shoji Hoshitoku, Hironori Tsubota, Yasuhiro Kashima
  • Patent number: 10321566
    Abstract: A printed wiring board according to an aspect of the present invention includes an insulating resin, a plated copper formed on a front surface side of the insulating resin, and a plated copper formed on a back surface side of the insulating resin. The plated copper and the plated copper are electrically connected via a plated copper that fills a through hole penetrating the insulating resin from the front surface side to the back surface side. Furthermore, the through hole includes a conical section whose opening diameter decreases from the front surface side to the back surface side of the insulating resin, and a cylindrical section that communicates with the conical section at a bottom surface of the conical section.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 11, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Yasuyuki Hitsuoka
  • Patent number: 10320145
    Abstract: In various embodiments, laser apparatuses include thermal bonding layers between various components and sealing materials for preventing or retarding movement of thermal bonding material out of the thermal bonding layers.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 11, 2019
    Assignee: TERADIODE, INC.
    Inventors: Parviz Tayebati, Michael Deutsch
  • Patent number: 10304800
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Weiming Chris Chen, Ting-Yu Yeh, Chia-Hsin Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Patent number: 10298803
    Abstract: An scanning lens to scan a document image includes a lens and a retainer to retain the lens bonded and fixed to the retainer by an adhesive. Conditional formula (1), or both conditional formula (2) and conditional formula (3) below are satisfied: ? Vb = 0 , ( 1 ) 0 ? | ? large / ? small × ( ? i n ? Vp i - ? i n ? Vm i ) / ( ? i n ? Vp i + ? i n ? Vm i ) | < 3.5 ? ? ( i = 1 , 2 , … ? ? n ) , ? ? and ( 2 ) ? 0 < Vb / Va < 0.5 .
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Takuya Nagano
  • Patent number: 10269758
    Abstract: A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Zhihua Zou, Sudip M. Thomas
  • Patent number: 10236242
    Abstract: A package substrate is provided. The package substrate includes a dielectric layer and a passive component embedded in the dielectric layer and contacting the dielectric layer. A circuit layer is embedded in the dielectric layer and has a first surface aligned with a second surface of the dielectric layer. A conductive structure is embedded in the dielectric layer and electrically connected to the passive component and the circuit layer. A chip package is also provided.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 19, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Ta-Jen Yu
  • Patent number: 10153250
    Abstract: A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stefano Oggioni, Thomas Brunschwiler, Gerd Schlottig
  • Patent number: 10121738
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Patent number: 10049962
    Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Edward Fuergut, Joachim Mahler
  • Patent number: 10021776
    Abstract: A component carrier includes a multi-layer carrier body having a substrate containing a structured functional. The substrate extends both laterally and also at least partially above and below the functional region. Alternatively, or in addition, the substrate extends both laterally and also completely above and/or below the functional region. Alternatively, or in addition, the substrate or a further region is arranged in or extends into the functional region.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: July 10, 2018
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Axel Pecina
  • Patent number: 9905534
    Abstract: A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces. The first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip are vertical to each other.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 27, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Masato Mikami, Takanori Sekido
  • Patent number: 9899325
    Abstract: In various embodiments a method of forming a device is provided. The method includes forming a metal layer over a substrate and forming at least one barrier layer. The forming of the barrier layer includes depositing a solution comprising a metal complex over the substrate and at least partially decomposing of the ligand of the metal complex.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 20, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Ravi Joshi
  • Patent number: 9870999
    Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 16, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Walter Kleemeier, Paul Ferreira, Ronald K. Sampson
  • Patent number: 9837370
    Abstract: A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin
  • Patent number: 9837732
    Abstract: An electrical contact composite is described. The electrical contact composite has a substrate and an electrically conductive coating applied to the substrate, which coating is connected to an electrode. A metal contact element is connected to the electrode, which contact element is used to connect the conductive coating to a current/voltage source. Furthermore, at least one sprayed layer produced by means of a thermal spraying method, in particular gas dynamic cold spray, and is provided with at least one metal and/or metal alloy, the sprayed layer being arranged between the conductive coating and the contact element. The sprayed layer has a coefficient of thermal expansion that is between the coefficients of thermal expansion of the carrier and of the contact element. The sprayed layer can also be used as the electrode for the conductive coating.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: December 5, 2017
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Mitja Rateiczak, Bernhard Reul
  • Patent number: 9764430
    Abstract: Provided are a lead-free solder alloy which consists of Sb in an amount of more than 3.0% but 10% or less by mass, and the balance including Sn, and others.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 19, 2017
    Assignee: KOKI Company Limited
    Inventors: Atsushi Irisawa, Rie Wada
  • Patent number: 9768128
    Abstract: According to one embodiment, a chip is described comprising a transistor level, a semiconductor region in, below, or in and below the transistor level, a test signal circuit configured to supply a test signal to the semiconductor region, a determiner configured to determine a behavior of the semiconductor region in response to the test signal and a detector configured to detect a change of geometry of the semiconductor region based on the behavior and a reference behavior of the semiconductor region in response to the test signal.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: September 19, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kuenemund, Jan Otterstedt, Christoph Saas
  • Patent number: 9741676
    Abstract: A lead-free solder alloy having a low melting temperature and low yield strength is disclosed. The solder alloy includes 5.0-20.0 wt. % of indium (In), 1.0-5.0 wt. % of silver (Ag), 0.25-2.0 wt. % of copper (Cu), 0.1-0.5 wt. % of zinc (Zn), and a remainder of tin (Sn). In implementations, a sulfur compound may be included in a concentration of 100 ppm to 500 ppm in the alloy to prevent oxidation of zinc and indium on the surface of the alloy. The solder alloy is particularly useful for but not limited to solder on pad applications in first level interconnect semiconductor device packaging.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 22, 2017
    Assignee: Indium Corporation
    Inventors: Jianguo Luo, Ning-Cheng Lee
  • Patent number: 9731370
    Abstract: A semiconductor module includes a substrate having a metallized first side and a metallized second side opposing the metallized first side. A semiconductor die is attached to the metallized first side of the substrate. A plurality of cooling structures are welded to the metallized second side of the substrate. Each of the cooling structures includes a plurality of distinct weld beads disposed in a stacked arrangement extending away from the substrate. The substrate can be electrically conductive or insulating. Corresponding methods of manufacturing such semiconductor modules and substrates with such welded cooling structures are also provided.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andre Uhlemann, Alexander Herbrandt
  • Patent number: 9716019
    Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 25, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Zhaohui Ma, Aibin Yu
  • Patent number: 9716115
    Abstract: A flexible display and method of manufacturing the same are disclosed. In one aspect, the display includes a flexible substrate including first concave bent portion and a pad formed over the first concave bent portion of the flexible substrate and including a second concave bent portion overlapping the first concave bent portion. The display further includes a connection pin electrically connected to the second concave bent portion. The connection pin has a central portion and a boundary portion surrounding the central portion. The height of the central portion is greater than that of the boundary portion.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: July 25, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong-Koo Her
  • Patent number: 9685423
    Abstract: The invention relates to a chip arrangement (18) comprising a terminal substrate (12) and a plurality of semiconductor substrates (1) which are arranged on the terminal substrate, in particular chips, wherein terminal faces (5) arranged on a contact surface of the chips (1) are connected to terminal faces on a contact surface (14) of the terminal substrate (12), wherein the chips (1) extend parallel with a lateral edge and transversally with their contact surface to the contact surface of the terminal substrate (12), wherein vias (13) are arranged in the terminal substrate, which connect external contacts (15) arranged on an external contact side to terminal faces formed as internal contacts (14) on the contact surface of the terminal substrate, wherein terminal faces of the chips, which are arranged adjacent to the lateral edge, are connected to the internal contacts of the terminal substrate by way of a re-melted solder material deposit (16).
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: June 20, 2017
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventor: Ghassem Azdasht
  • Patent number: 9679862
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a semiconductor chip. The semiconductor chip includes a surface facing the plurality of conductive traces and a plurality of conductive pads on the surface and correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 9640508
    Abstract: An electrical apparatus includes a first electrical component; a second electrical component; and an In—Sn—Ag alloy connecting the first electrical component and the second electrical component, the In—Sn—Ag alloy containing AgIn2 and Ag2In, a Ag2In content being lower than a AgIn2 content.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 2, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Taiki Uemura, Kozo Shimizu, Seiki Sakuyama
  • Patent number: 9627341
    Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 18, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Peter Brockhaus, Uwe Koeckritz
  • Patent number: 9607959
    Abstract: An example packaging device includes a substrate having an integrated circuit die mounting region disposed thereon. A plurality of microstructures are disposed proximate a side of the integrated circuit die mounting region. The plurality of microstructures each include an outer insulating layer over a conductive material. An example packaged semiconductor device includes a substrate having an integrated circuit die mounting region disposed thereon. A plurality of columnar microstructures are disposed on the substrate perpendicular to a major surface of the substrate and proximate a side of the integrated circuit die mounting region. An underfill material is disposed between the substrate and the integrated circuit die.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Yu-Feng Chen, Chen-Shien Chen
  • Patent number: 9601475
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: March 21, 2017
    Assignee: Intel Deutschland GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • Patent number: 9583419
    Abstract: Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: February 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Philip J. Ireland
  • Patent number: 9533880
    Abstract: A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 3, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Steven S. Nasiri, Anthony F. Flannery, Jr.
  • Patent number: 9508623
    Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: November 29, 2016
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
  • Patent number: 9508628
    Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh
  • Patent number: 9491867
    Abstract: A wiring substrate includes: a substrate body made of ceramic and having a front surface and a rear surface, each having a rectangular shape in a plan view, a plurality of rear surface electrodes formed on the rear surface of the substrate body, a frame-shaped conductive portion provided on the front surface side of the substrate body, and a via conductor penetrating the substrate body and establishing electric connection between the plurality of rear surface electrodes and the frame-shaped conductive portion. A part of the rear surface is exposed between the plurality of rear surface electrodes and each side of the rear surface of the substrate body. On the rear surface of the substrate body, at least one projecting wiring is formed between each of the plurality of rear surface electrodes and each of a corresponding pair of the sides that intersect with each other.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 8, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Takashi Kurauchi, Yoshitaka Yoshida, Kazushige Akita
  • Patent number: 9459287
    Abstract: The invention provides a guide plate for a probe card including a silicon substrate including a surface and a through-hole, an edge part of the through-hole, and a curved-face part. The through-hole is configured to guide a probe and includes an inner wall face. The edge part of the through-hole is constituted by the surface of the silicon substrate and the inner wall face of the through-hole. The curved-face part is formed on the edge part and formed of a silicon dioxide film.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 4, 2016
    Assignees: JAPAN ELECTRONIC MATERIALS CORPORATION, SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Teppei Kimura, Akinori Shiraishi, Kosuke Fujihara
  • Patent number: 9326373
    Abstract: A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: April 26, 2016
    Assignee: FINISAR CORPORATION
    Inventors: Henry Meyer Daghighian, Steven C. Bird
  • Patent number: 9076754
    Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending beyond edges of the first die. A first Thermal Interface Material (TIM) is overlying and contacting a top surface of the first die. A heat sink has a first bottom surface over and contacting the first TIM. A second TIM is overlying and contacting the second portion of the second die. A heat dissipating ring is overlying and contacting the second TIM.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Szu-Po Huang, Kim Hong Chen, Shin-Puu Jeng
  • Patent number: 9035465
    Abstract: Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons, Louis L. Hsu
  • Patent number: 9024452
    Abstract: A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 5, 2015
    Assignee: STS Semiconductor & Telecommunications Co., Ltd.
    Inventor: Jung Hwan Chun
  • Patent number: 8987922
    Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Hung-Jen Lin
  • Patent number: 8987064
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 24, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8969143
    Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
  • Patent number: 8963197
    Abstract: An LED package includes a package body having a well formed in its upper surface, where the well is configured to receive a light emitting chip. An optical lens is disposed above the package body and includes a hollow dome structure located above and encompassing the lateral extent of the light emitting chip within the well of the package body. In one implementation, the package body and the optical lens collectively include at least one protrusion and concave, where the protrusion is aligned with the concave so that the optical lens mates with the package body, thereby causing the optical lens to self align with the package body. In another implementation, a protruding inner portion of the upper surface of the package body mates with the hollow dome structure, achieving a similar purpose. Consequently, generation of an eccentric fault between the optical lens and the package body is prevented.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Myung Soo Han, Seung Ho Jang, Won Seok Choi
  • Patent number: 8957512
    Abstract: An embodiment of an interposer is disclosed. For this embodiment of the interposer, a first circuit portion is created responsive to a first printing region. A second circuit portion is created responsive to a second printing region. The interposer has at least one of: (a) a length dimension greater than a maximum reticle length dimension, and (b) a width dimension greater than a maximum reticle width dimension.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Xilinx, Inc.
    Inventor: Toshiyuki Hisamura
  • Patent number: 8912646
    Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 16, 2014
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Michael A. Stuber, Stuart B. Molin, Mark Drucker, Peter Fowler
  • Patent number: 8912659
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyeong Seok Choi
  • Patent number: 8907354
    Abstract: The present disclosure relates to an optoelectronic device, in particular to an arrangement for contacting an optoelectronic device. The optoelectronic device (200) includes an elastic electrode (208). A method for forming the elastic electrode (208) is described.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andrew Ingle
  • Patent number: 8901753
    Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Patent number: 8896110
    Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Wei Hu, Zhizhong Tang, Syadwad Jain, Rajen S. Sidhu