Abstract: A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.

Abstract: The present disclosure provides a novel form of a display device which enables semiconductor light emitting elements having a vertical structure to be assembled onto a substrate and then wiring process to be performed stably without any change to the position of the elements during post-processing.

Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Abstract: There is provided a flexible electronic structure for bonding with an external circuit. The flexible electronic structure comprising: a flexible body having a first surface, the flexible body comprising at least one electronic component; at least one contact element configured to bond with the external circuit, the at least one contact element operatively coupled with the at least one electronic component and provided at the first surface of the flexible body, and arranged to operably interface with the external circuit after bonding, and at least one support element provided at the first surface of the flexible body, each support element arranged to contact a corresponding surface element disposed on a first surface of an external structure comprising the external circuit.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.

Abstract: A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Abstract: A quantum computing system can include a first substrate including one or more quantum control devices. The quantum computing system can include a second substrate including one or more quantum circuit elements. The quantum computing system can include one or more tin contact bonds formed on the first substrate and the second substrate. The tin contact bonds can bond the first substrate to the second substrate. The tin contact bonds can be or can include tin, such as a tin alloy.

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips, and electrical connection structures. The interposer includes a first connection structure having a first redistribution conductor, second connection structures each having a second redistribution conductor, third connection structures each having a third redistribution conductor, and a passivation layer filling spaces between the first to third connection structures. The first semiconductor chip is disposed on the interposer to overlap the first connection structure and some third connection structures. The second semiconductor chip is disposed on the interposer to overlap some second connection structures and third connection structures. The electrical connection structures are electrically connected to the first and second chips.

Abstract: Disclosed in the present application are a camera module, and a photosensitive assembly and a manufacturing method therefor. The photosensitive assembly comprises a circuit board, a photosensitive chip electrically connected to the circuit board, and a shaping member provided on the circuit board. A lower surface of the photosensitive chip is attached to the shaping member to form an accommodating space with the shaping member and the circuit board. The accommodating space is configured so that the photosensitive chip is bent downward during a process of assembling the photosensitive assembly. In this way, the photosensitive chip is bent into a shape adapted to the actual focal plane during the assembly process, so as to improve the imaging quality.

Abstract: A VCSEL/VECSEL array design is disclosed that results in arrays that can be directly soldered to a PCB using conventional surface-mount assembly and soldering techniques for mass production. The completed VCSEL array does not need a separate package and no precision sub-mount and flip-chip bonding processes are required. The design allows for on-wafer probing of the completed arrays prior to singulation of the die from the wafer. Embodiments relate to semiconductor devices, and more particularly to multibeam arrays of semiconductor lasers for high power and high frequency applications and methods of making and using the same.

Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.

Abstract: A composite integrated film includes a base member thin film having a base member first surface and a base member second surface facing each other, one or more penetration parts penetrating the base member first surface and the base member second surface of the base member thin film, one or more electrodes each including an electrical path part formed between the base member first surface and the base member second surface via the penetration part and an electrode surface in a planar shape formed on the base member second surface's side, and one or more elements provided on the base member first surface of the base member thin film and electrically connected to the electrodes, wherein the electrode surface and the base member second surface form a same flat surface.

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.

Abstract: A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.

Abstract: Discussed is a display device, including a substrate, a wiring electrode disposed on the substrate, a plurality of semiconductor light-emitting elements electrically connected to the wiring electrode, an anisotropic conductive layer disposed between the plurality of semiconductor light-emitting elements and formed of a mixture of conductive particles and an insulating material; and a buffer portion disposed on a lower surface of a semiconductor light-emitting element of the plurality of semiconductor light-emitting elements so as to allow the wiring electrode and the semiconductor light-emitting element to be spaced apart by a predetermined distance, and provided with at least one hole, wherein the mixture of the conductive particles and the insulating material is disposed inside the at least one hole, and the wiring electrode is electrically connected to the semiconductor light-emitting element through conductive particles disposed inside the at least one hole.

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors topographically aligned with the first die include a first density. The plurality of middle interconnectors topographically aligned with the second die include a second density different from the first density.

Abstract: Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate; an integrated circuit region formed in the semiconductor substrate; and a seal ring arranged in the semiconductor substrate and around the integrated circuit region and configured to protect the integrated circuit region, wherein the seal ring has a wavy structure.

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.

Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section vie

Abstract: An object is to provide a technique that can suppress wet-spreading of an adhesive used to bond a case and a metal base to each other and secure the height position of the adhesive required to fill a gap created between the case and the metal base. A semiconductor device includes a metal base, an insulating substrate arranged on the metal base, a semiconductor element mounted on the insulating substrate, and a case bonded on the metal base so as to surround side surfaces of the insulating substrate and the semiconductor element, in which a pair of metal oxide films having a protruding shape is provided on a peripheral edge portion of the metal base, and the case is bonded to the metal base by an adhesive arranged in a region between the metal oxide films in the pair.

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

Abstract: A composite structure includes a first surface and a second surface sandwiched together with a field array of individual and discrete pillars extending therebetween. The plurality of discrete pillars each have a tailored coefficient of thermal expansion and are designed to expand and contract over varying temperatures. The discrete pillars are specifically arranged within the composite structure to compensate for the shrinkage and expansion of different components of a microelectronic hybrid device, to reduce thermal expansion induced deformations imparted on facets of the microelectronic hybrid device under varying temperatures.

Abstract: Microelectronic devices may include first bond pads located proximate to, and distributed along, a first side of the microelectronic device. Other bond pads may be located proximate to, and distributed along, another side of the microelectronic device perpendicular to the first side. A first pitch of the first bond pads may be greater than another pitch of the other bond pads. When microelectronic devices are placed side by side, the bond pads on sides of the microelectronic devices proximate to one another may be interposed between one another in the direction parallel to the first shortest distance between adjacent first bond pads.

Abstract: An apparatus, system and method for dispensing underfill to components on a printed circuit board. The apparatus, system and method may include an underfill chamber having an input through which the printed circuit board is received; at least one dispensing robot capable of dispensing the underfill to the components; a lower heater suitable to substantially evenly heat at least half of or the entirety of an underside of the printed circuit board once the printed circuit board is within the underfill chamber; and an overhead heater capable of heating up to half of a topside of the printed circuit board once the printed circuit board is within the underfill chamber.

Abstract: A semiconductor device according to an embodiment includes a semiconductor layer, a metal layer, and a bonding layer provided between the semiconductor layer and the metal layer, the bonding layer including a plurality of silver particles, and the bonding layer including a region containing gold existing between the plurality of silver particles.

Abstract: An inductor structure is provided. A plurality of first and second conductive posts have end surfaces corresponding in profile to ends of first conductive sheets, respectively. As such, the profiles of the end surfaces of the first and second conductive posts are non-cylindrical so as to increase the contact area between the first conductive sheets and the first and second conductive posts, thereby improving the conductive quality and performance of the inductor. Further, since the first and second conductive posts are formed by stacking a plurality of post bodies on one another, the number and cross-sectional area of loops are increased so as to increase the inductance value. A method for fabricating the inductor structure, an electronic package and a fabrication method thereof, and a method for fabricating a packaging carrier are further provided.

Abstract: A method for bonding two confronting electronic devices together wherein the two electronic devices are initially temporarily coupled together using a room temperature process with a plurality of knife-edge microstructures on at least a first one of the electronic devices engaging portions of the a second one of the electronic devices. The room temperature process involves applying a relatively low compressive force or pressure between the two electronic devices compared to the forces or pressures used in convention flip-chip bonding. The first one of the electronic devices and the second one of the electronic devices also have traditional contact pads that are spaced from each other by a standoff distance when the devices are initially coupled together using the room temperature process. This allows for inspection of the two electronic devices while they are initially temporarily coupled together.

Abstract: A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

Abstract: A system includes a die with a first plurality of hybridization bumps extending therefrom, electrically connected to circuitry die. An external circuitry component with a second plurality of hybridization bumps extending therefrom, electrically connected to circuitry in the external circuitry component. The first plurality of hybridization bumps and the second plurality of hybridization bumps are pressed together for electrical communication between the die and the external circuitry component. The first plurality of hybridization bumps have a different material hardness from the second plurality of hybridization bumps. The first plurality of hybridization bumps have a different bump diameter from that of the second plurality of hybridization bumps.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.

Abstract: Apparatus and associated methods relate to a pick & place system that uses a magnetic core for both magnetic coupling with an assembly component and heating of the assembly component. The magnetic core has a component engagement surface configured to magnetically and thermally engage the component. A controller is configured to provide both AC current and DC current to an inductive coil wound about the magnetic core. DC current provided to the inductive coil induces a magnetic field within the magnetic core, thereby magnetically attracting the component when engaged with the component engagement surface. AC current provided to the magnetic core inductively heats the magnetic core, thereby heating the component when engaged with the component engagement surface.

Abstract: A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads, and an open cavity. A bridge die is in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, a power delivery bridge pad between the first plurality of bridge pads and the second plurality of bridge pads, and conductive traces. A first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads. A second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads. A power delivery conductive line is coupled to the power delivery bridge pad.

Abstract: A circuit board, including: a substrate; a first line layer, a first protective layer, a first conductive ink layer and a first conductive layer successively formed on the substrate; and a second line layer, a second protective layer, a second conductive ink layer and a second conductive layer successively formed on a second face opposite a first face. The first protective layer includes at least one first opening for exposing a first grounding line of the first line layer; and the orthographic projection of the first conductive ink layer on the substrate covers the orthographic projection of the first opening on the substrate. The second protective layer includes at least one second opening for exposing a second grounding line of the second line layer; and the orthographic projection of the second conductive ink layer on the substrate covers the orthographic projection of the second opening on the substrate.

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract: An electrically conductive hybrid membrane, including a solid membrane substrate including a curable material; and electrically conductive particle disposed on the solid membrane substrate, wherein the solid membrane substrate has an elastic modulus of about 10 MPa to about 1000 MPa, and the electrically conductive particle is exposed on both sides of the solid membrane substrate.

Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.

Abstract: A wafer chip scale package (WCSP) includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads exposed by a passivation layer, and a top dielectric layer over the passivation layer. A dielectric layer bounded (DLB) cavity formed in the top dielectric layer includes a first cavity being a center through-cavity bounded by a second cavity being a partial through-cavity, the DLB cavity is lined with a seed layer. A capping dielectric layer that covers the DLB cavity except for an aperture over the first cavity. A cavity metal that is generally configured as an integral structure of continuous metal material having no interfaces is for filling the DLB cavity to form a metal filled cavity including over the aperture that has an electrical connection to the die bond pads. A solder ball over the cavity metal is positioned over the aperture.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: A pressing method operatively associated with a press apparatus includes: providing a first substrate connected with a flexible printed circuit board onto a stage; providing a second substrate onto the stage; arranging the flexible printed circuit board on the second substrate; pressing a pad electrode-free area of the flexible printed circuit board; and pressing first pad electrodes of the flexible printed circuit board and second pad electrodes of the second substrate.

Abstract: An apparatus and method for semiconductor device (such as semiconductor die or die) bonding. The apparatus has a bonding assembly with a bonding head having a bonding tool for holding a semiconductor device; and a bonding head actuation mechanism for actuating the bonding tool horizontally planarly to align the semiconductor device relative to a bonding location of a substrate while the semiconductor device remains above the bonding location. The bonding assembly has a bonding assembly actuator for actuating the bonding head vertically to pick the semiconductor device and to bond the semiconductor device at the bonding location. The apparatus has a vision assembly with alignment cameras for capturing reference views of the semiconductor device and bonding location for aligning the semiconductor device relative to the bonding location, and a vision assembly actuation mechanism for actuating the alignment cameras to position the alignment cameras between the bonding tool and bonding location.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.

Abstract: A material sheet is provided having antenna patterns that include first and second coupling portions that are transported toward a mounting position, and an adhesive member that is disposed on the material sheet before reaching the mounting position. At a pickup position, a mounting device picks up an RFIC module including an RFIC chip and first and second terminal electrodes connected to the RFIC chip. At the mounting position, the mounting device mounts the picked-up RFIC module onto the adhesive member on the material sheet so that the first coupling portion and the first terminal electrode face each other and so that the second coupling portion and the second terminal electrode face each other.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (?m) to about 30 ?m.