Abstract: A method according to one embodiment includes depositing a dielectric hard mask layer above a polymer mask under-layer; forming a photoresist mask above the hard mask layer; transferring the image of the photoresist mask onto the hard mask layer using reactive ion etching, thereby defining a hard mask; determining that a critical dimension bias of the hard mask is within or outside a specification; and changing a level of an input source power used during a subsequent reactive ion etching step to move the critical dimension bias towards a target critical dimension bias when the critical dimension bias of the hard mask is outside the specification. Additional embodiments are also disclosed.

Abstract: A method of increasing the operating life of a semiconductor device that is to be used in a harsh ionizing radiation environment including determining heating criteria for annealing the device; installing the device in an electronic apparatus; and heating the installed device with a local heating source in accordance with the heating criteria.

Abstract: A chip quality determination method includes the steps of (a) determining the continuity of defective chips in at least four directions of an X-axis and a Y-axis on a wafer based on the wafer test result of determining the acceptability of chips arranged in a matrix in the four directions on the wafer, and dividing the defective chips into one or more defective groups so that successive ones of the defective chips are in the same defective group; (b) calculating a quality determination index of each of one or more determination target wafer periphery neighboring chips among wafer periphery neighboring chips located within a predetermined range from the periphery of the wafer based on the distance from a corresponding one of the defective groups; and (c) determining the quality of the determination target wafer periphery neighboring chips by comparing the quality determination indexes thereof with a preset threshold.

Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.

Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: According to the embodiments, a distribution of a recess portion shape is calculated based on a result obtained by measuring the recess portion shape of a first projection and recess pattern formed on a surface of a template. Next, a distribution of an application amount of a curing agent to a processing target layer is calculated based on the distribution of the recess portion shape, and the curing agent is applied to the processing target layer based on this distribution of the application amount of the curing agent. Next, a second projection and recess pattern is formed by transferring the first projection and recess pattern onto the curing agent by causing the curing agent to cure in a state where the first projection and recess pattern is in contact with the curing agent.

Abstract: An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card.

Abstract: With a die bonder or a bonding method, the die is adsorbed by the collet, the dicing tape to which the die is adsorbed is thrust up, the die adsorbed by the collet, and thrust up is peeled from the dicing tape, and the peeled die is bonded to the substrate. When the decrease in the air leak flow rate through the gap between the collet and the die upon the thrust up is smaller than the decrease in the normal peel by a predetermined amount, it is judged that a deflection occurs in the die.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A test map classification method includes modifying test data by converting to a test map including a wafer identifier, a coordinate, and data on whether a predetermined failure item occurs; calculating similarities of wafer pairs in the test map; performing similarity filtering to reset all the similarities, except for at least one similarity, on the basis of a predetermined wafer; determining whether there are similar wafers by comparing the filtered similarities with a reference value; and classifying spatial patterns using a similar relationship between the wafer pairs when there are similar wafers.

Abstract: In a disclosed good chip classifying method capable of classifying the good chips on a wafer, defective chips are divided into defective groups so that the defective chips contiguous to each other are placed into the same defective group based on the wafer test results; the defective group is judged as a defective chip concentrated distribution area when the number of the defective chips exceeds the prescribed value; a defective chip concentrated distribution nearby area including all the defective chips in the defective chip concentrated distribution area and nearby good chips is formed; and the good chips in the defective chip concentrated distribution nearby area are classified to have a chip index based on four directions (X and Y axis directions) on which the defective chips in the defective chip concentrated distribution area are disposed.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.

Abstract: A wafer level marking system is provided including: providing a wafer, a wafer frame, and a support tape; mounting the wafer and the wafer frame on the support tape; and marking the wafer through the support tape.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A system for imposing and analyzing surface acoustic waves in a substrate to determine characteristics of the substrate is disclosed. Optical elements and arrangements for imposing and analyzing surface acoustic waves in a substrate are also disclosed. NSOM's, gratings, and nanolight elements may be used to impose surface acoustic waves in a substrate and may also be used to measure transient changes in the substrate due to the passage of surface acoustic waves therethrough.

Abstract: Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.

Abstract: There is provided a method for producing a photoelectric conversion device in which an object to be processed is processed by directing a light beam to a position determined based on information including temperature information and distortion information acquired in advance. There is also provided a light beam irradiation processing apparatus including a control portion capable of controlling a light beam generating portion and a drive portion in such a manner that a light beam can be directed to a position determined based on information including temperature information acquired by a temperature information acquiring portion and distortion information stored therein.

Abstract: A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and that is to be used in a device fabrication process or an inspection process including a process of controlling a position of the SOI wafer on the basis of intensity of reflected light from the SOI wafer when the SOI wafer is irradiated with light having a wavelength ?. The method includes the steps of: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength ? of the light for use in the process of controlling the position that is to be implemented on the SOI wafer after manufacturing; and fabricating the SOI wafer having the SOI layer formed on the buried insulator layer having the designed thickness.

Abstract: A method for repairing a semiconductor structure having a current-leakage issue includes finding a semiconductor structure having a current-leakage issue through application of a test voltage from an electric test device and applying an electric power stress to the semiconductor structure to melt a stringer or a bridge between two conductive elements or to allow the stringer or the bridge to be oxidized.

Abstract: A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed.

Abstract: A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.

Abstract: A hollow cathode system is provided for plasma generation in substrate plasma processing. The system includes an electrically conductive member shaped to circumscribe an interior cavity, and formed to have a process gas inlet in fluid communication with the interior cavity, and formed to have an opening that exposes the interior cavity to a substrate processing region. The system also includes a first radiofrequency (RF) power source in electrical communication with the electrically conductive member so as to enable transmission of a first RF power to the electrically conductive member. The system further includes a second RF power source in electrical communication with the electrically conductive member so as to enable transmission of a second RF power to the electrically conductive member. The first and second RF power sources are independently controllable with regard to frequency and amplitude.

Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.

Abstract: A polishing method and a polishing apparatus particularly suitable for finishing a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that a surface of a substrate of a compound semiconductor containing an element of Ga can be flattened with high surface accuracy within a practical processing time. In the presence of water (232) such as weak acid water, water with air dissolved therein, or electrolytic ion water, a surface of a substrate (142) made of a compound semiconductor containing either one of Ga, Al, and In and the surface of a polishing pad (242) having an electrically conductive member (264) in an area of the surface which is held in contact with the substrate (142) are relatively moved while being held in contact with each other, thereby polishing the surface of the substrate (142).

Abstract: A light emitting device is produced by depositing a layer of wavelength converting material over the light emitting device, testing the device to determine the wavelength spectrum produced and correcting the wavelength converting member to produce the desired wavelength spectrum. The wavelength converting member may be corrected by reducing or increasing the amount of wavelength converting material. In one embodiment, the amount of wavelength converting material in the wavelength converting member is reduced, e.g., through laser ablation or etching, to produce the desired wavelength spectrum.

Abstract: An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Abstract: A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator.

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one tot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: A method of manufacturing a semiconductor module is provided. The method includes forming semiconductor chips on a bare substrate, performing a burn-in process on the bare substrate including the semiconductor chips, sorting semiconductor chips that exceed a predetermined level of operability determined by testing electrical driving in the semiconductor chips on the burned-in bare substrate, separating the semiconductor chips from one another by cutting the bare substrate, and directly mounting the module semiconductor chips on a module substrate.

Abstract: A method and system for repairing photomasks is disclosed. A scanning electron microscope (SEM) is used to identify, measure, and correct defects. The SEM is operated in multiple modes, including a measuring mode and a repair mode. The repair mode is of higher landing energy and exposure time than the measuring mode, and induces shrinkage in the photoresist to correct various features, such as vias that are too small.

Abstract: A light-emitting diode includes at least one light-emitting diode chip, at least one control device, wherein each of the light-emitting diode chips is electrically connected to one of the at least one control devices, each of the at least one control devices including a data storage device in which brightness data for each light-emitting diode chip which is connected to the control device is stored, and the control device drives the connected light-emitting diode chip with a current which is selected according to stored brightness data for the light emitting-diode chip.

Abstract: Apparatus (1) for manufacturing solar cell matrices includes several stringers (2) for forming strings from solar cells, a lay-up and interconnection station (5) for arranging and interconnecting the strings to form a solar cell matrix, and a transportation system (3) for transferring the strings from the stringers (2) to the lay-up and interconnection station (5), wherein the stringers (2) are arranged perpendicular to the direction of flow of the transportation system (3), or in an acute angle to an axis perpendicular to the direction of flow of the transportation system (3). Furthermore, a process for operating such apparatus (1), wherein the several stringers (2) are controlled such that collision between different strings is avoided in the transportation system (3).

Abstract: A method and system for repairing photomasks is disclosed. A scanning electron microscope (SEM) is used to identify, measure, and correct defects. The SEM is operated in multiple modes, including a measuring mode and a repair mode. The repair mode is of higher landing energy and exposure time than the measuring mode, and induces shrinkage in the photoresist to correct various features, such as vias that are too small.

Abstract: A new method is provided for the creation of a hole through a layer of insulating material. The method provides for combining a feed-forward method with a feed backward method and a high-polymer based hole profile, in order to establish a hole of a constant Critical Dimension for the hole bottom, making the CD of the hole bottom independent of the CD of the opening created through the overlying developed layer of photoresist and independent of the thickness of the layer of insulator material after CMP has been applied to the surface of the insulation layer.

Abstract: A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask 109 is applied to the recorded image and unmasked portions 111 of the image are further processed by averaging. The unmasked portions 111 are selected such that they include memory portions of the wafer.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: A photodetector array includes a plurality of photodetector cells such as avalanche photodiodes and readout circuits. An array self-tester tests a dark count or other performance characteristic of the cells. The test is performed in connection with the manufacture of the array or following the installation of the array in a detection system.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.

Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

Abstract: InyGa1-yN (0<y<1) layers whose principal surface is a non-polar plane or a semi-polar plane are formed by an MOCVD under different growth conditions. Then, the relationship between the growth temperature and the In supply mole fraction in a case where the pressure and the growth rate are constant is determined based on a growth condition employed for formation of InxGa1-xN (0<x<1) layers whose emission wavelengths are equal among the InyGa1-yN layers. Then, a saturation point is determined on a curve representing the relationship between the growth temperature and the In supply mole fraction, the saturation point being between a region where the growth temperature monotonically increases according to an increase of the In supply mole fraction and a region where the growth temperature saturates. Under a growth condition corresponding to this saturation point, an InxGa1-xN layer is grown.

Abstract: A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Abstract: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated.

Abstract: An apparatus for dispensing fluid during semiconductor substrate processing operations comprises an enclosure having a first side and a second side. The enclosure comprises a first processing station and a second processing station. The second processing station is positioned adjacent to the first processing station. In addition, the substrate processing apparatus includes a first dispense arm configured to deliver a fluid to the first processing station wherein the first dispense arm is positioned between the first side and the first processing station and a second dispense arm configured to deliver the fluid to the second processing station wherein the second dispense arm is positioned between the second side and the second processing station. The substrate processing apparatus also comprises a first rinse arm configured to deliver a rinsing fluid to the first processing station and a second rinse arm configured to deliver the rinsing fluid to the second processing station.

Abstract: In a substrate processing control method, a first process acquires a first-reflectance-spectrum of a beam reflected from the first-fine-structure and a second-reflectance-spectrum of a beam reflected from the second-fine-structure for each of varying-pattern-dimensions of the first-fine-structure when the pattern-dimension of the first-fine-structure is varied. A second process acquires reference-spectrum-data for each of the varying-pattern-dimensions of the first-fine-structure by overlapping the first-reflectance-spectrum with the second-reflectance-spectrum. A third process actually measures beams reflected from the first and the second-fine-structure, respectively, after irradiating light beam on to the substrate and acquiring reflectance-spectrums of the actual-measured beams as actual-measured spectrum data.