Abstract: A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.

Abstract: The present invention may include performing a first measurement on a wafer of a first lot of wafers via an omniscient sampling process, calculating a first set of process tool correctables utilizing one or more results of the measurement performed via an omniscient sampling process, randomly selecting a set of field sampling locations of the wafer of a first lot of wafers, calculating a second set of process tool correctables by applying an interpolation process to the randomly selected set of field sampling locations, wherein the interpolation process utilizes values from the first set of process tool correctables for the randomly selected set of field sampling locations in order to calculate correctables for fields of the wafer of the first lot not included in the set of randomly selected fields, and determining a sub-sampling scheme by comparing the first set of process tool correctables to the second set of correctables.

Abstract: Described herein are methods and systems for chamber matching in a manufacturing facility. A method may include receiving a first chamber recipe advice for a first chamber and a second chamber recipe advice for a second chamber. The chamber recipe advices describe a set of tunable inputs and a set of outputs for a process. The method may further include adjusting at least one of the set of first chamber input parameters or the set of second chamber input parameters and at least one of the set of first chamber output parameters or the set of second chamber output parameters to substantially match the first and second chamber recipe advices.

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) path delay test circuit and at least a portion of a critical path in one of its layers. The test circuit includes a plurality of inputs, outputs, a flip-flop coupled to the at least a portion of the critical path and a multiplexer coupled to the flip-flop and to a second layer of the IC. The test circuit further includes a control element such that path delay testing of the IC may be conducted on a layer-by-layer basis.

Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device.

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

Abstract: Among other things, one or more techniques for creating an array model for analog device modeling are provided. In an embodiment, the array model represents a mean value or a standard deviation value of an analog device characteristic for an analog device based on a physical location of the analog device within a circuit layout, where the physical location is identified using a physical set of coordinates. The physical set of coordinates maps to an array set of coordinates of the array model. In this manner, a mean value and a standard deviation value are obtainable from the array model using the array set of coordinates. The mean value and the standard deviation value are usable to model the analog device, and thus a circuit within which the analog device is used, to obtain a more accurate or realistic prediction of operation or behavior, for example.

Abstract: In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.

Abstract: A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.

Abstract: A method for generating a pattern of a mask used for an exposure apparatus through a calculation by a processor includes applying, to a target main pattern, a reference map of a characteristic value of an image of a representative main pattern with respect to a position of a representative auxiliary pattern calculated for each of a plurality of positions while the position of the representative auxiliary pattern with respect to the representative main pattern is changed and calculating a map of the characteristic value of the image of the target main pattern with respect to a position of an auxiliary pattern, and determining the position of the auxiliary pattern by using data of the map of the characteristic value of the image of the target main pattern and generating a pattern of a mask including the target main pattern and the determined auxiliary pattern.

Abstract: Dynamic pool reallocation performed by the following steps: (i) defining a plurality of resource pools including a first pool and a second pool, where each resource pool has a plurality of assigned resources; (ii) receiving a plurality of jobs to be executed; (iii) for each job of the plurality of jobs, assigning a respective resource pool, of the plurality of resource pools, to be used in completing the job; (iv) determining a preliminary schedule for executing the jobs on their respective resource pools; (v) determining whether the preliminary schedule will cause any jobs to miss service level agreement (SLA) deadlines corresponding to the job; (vi) executing the plurality of jobs on their respectively assigned resource pools; and (vii) re-assigning first resource from the second pool to the first pool during at least some of the time of the execution of the first job by the first resource pool.

Abstract: In accordance with certain embodiments, patches with replacement light-emitting elements thereon are utilized to repair lighting-system fault locations.

Abstract: Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model.

Abstract: Improvement in linearity is achieved at low costs in a power amplifier module employing an envelope tracking system. The power amplifier module includes a first power amplifier circuit that amplifies a radio frequency signal and that outputs a first amplified signal, a second power amplifier circuit that amplifies the first amplified signal on the basis of a source voltage varying depending on amplitude of the radio frequency signal and that outputs a second amplified signal, and a matching circuit that includes first and second capacitors connected in series between the first and second power amplifier circuit and an inductor connected between a node between the first and second capacitors and a ground and that decreases a gain of the first power amplifier circuit as the source voltage of the second power amplifier circuit increases.

Abstract: Methods for testing a special pattern and testing a probe card defect in wafer testing are provided. In the method for testing the special pattern, a wafer is divided into multiple testing partitions, in which each of the testing partitions includes multiple dies. The dies in each testing partition of the wafer are respectively tested by multiple sites of the probe card to obtain a testing map. Then, a number of the dies having defects and a number of the dies without defect within each of the testing partitions in the testing map are accumulated to construct chi-square test and calculate a maximum P-value. Finally, it is determined whether a minimum of the maximum P-values of all of the testing partitions is smaller than a certain predetermined threshold. If the minimum is smaller than the threshold, it is determined that the testing map of the wafer contains the special pattern.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: A method and apparatus for investigating a chemical-based event inside a vehicle without significant delay. A number of samples of air are collected at a number of locations inside the vehicle in response to a detection of the chemical-based event inside the vehicle. A number of chemical profiles for the number of samples are generated on-site using a portable chemical profiling device. A probable cause of the chemical-based event is identified using at least one of the number of chemical profiles.

Abstract: Dynamic pool reallocation performed by the following steps: (i) defining a plurality of resource pools including a first pool and a second pool, where each resource pool has a plurality of assigned resources; (ii) receiving a plurality of jobs to be executed; (iii) for each job of the plurality of jobs, assigning a respective resource pool, of the plurality of resource pools, to be used in completing the job; (iv) determining a preliminary schedule for executing the jobs on their respective resource pools; (v) determining whether the preliminary schedule will cause any jobs to miss service level agreement (SLA) deadlines corresponding to the job; (vi) executing the plurality of jobs on their respectively assigned resource pools; and (vii) re-assigning first resource from the second pool to the first pool during at least some of the time of the execution of the first job by the first resource pool.

Abstract: Methods and systems for determining a position of inspection data with respect to a stored high resolution die image are provided. One method includes aligning data acquired by an inspection system for alignment sites on a wafer with data for predetermined alignment sites. The predetermined alignment sites have a predetermined position in die image space of a stored high resolution die image for the wafer. The method also includes determining positions of the alignment sites in the die image space based on the predetermined positions of the predetermined alignment sites in the die image space. In addition, the method includes determining a position of inspection data acquired for the wafer by the inspection system in the die image space based on the positions of the alignment sites in the die image space.

Abstract: In performing a programmed-point inspection of a circuit pattern using a review SEM, stable inspection can be performed while suppressing the generation of a false report even when a variation in a circuit pattern to be inspected is large. SEM images that are obtained by sequentially imaging a predetermined circuit pattern using the review SEM are stored into a storage unit. Images that meet a set condition are selected from the stored SEM images, and averaged to create an average image (GP image). By performing pattern check by GP comparison using this GP image, an inspection can be performed while suppressing the generation of a false report even when a variation in the circuit patterns is large.

Abstract: A potential trouble can be in advance suppressed by analyzing a defect of a wafer. A defect analyzing apparatus of analyzing a defect of a substrate includes an imaging unit configured to image target substrates; a defect feature value extracting unit configured to extract a defect feature value in a surface of the substrate based on the substrate image; a defect feature value accumulating unit configured to calculate an accumulated defect feature value with respect to the substrates to create an accumulation data AH; a defect determination unit configured to determine whether the accumulated defect feature value exceeds a preset critical value; and an output display unit configured to output a determination result from the defect determination unit.

Abstract: A method for calculating leakage of a circuit including a plurality of transistors includes simulating a three-dimensional model of the circuit, wherein the simulating accounts for a subset of the plurality of the transistors that includes less than all of the plurality of transistors, and calculating the leakage in accordance with the three-dimensional model.

Abstract: A method for certifying an inspection system using a calibrated surface, comprising: acquiring a calibrated list from said calibrated surface, with said calibrated list comprising information about features located on said calibrated surface; inspecting said calibrated surface with said inspection system to generate an estimated list, with said estimated list comprising information about features located on said calibrated surface; generating a matched list by searching for the presence of one or more calibrated features in said estimated list, wherein said calibrated features are listed in said calibrated list; computing an estimated characteristic parameter from said matched list, wherein said estimated characteristic parameter quantifies features in said matched list having a unifying characteristic; and comparing said estimated characteristic parameter with a calibrated characteristic parameter, wherein said calibrated characteristic parameter quantifies features in said calibrated list having said unifyi

Abstract: A method for producing a substrate having an irregular concave and convex surface for scattering light includes: manufacturing a substrate having the irregular concave and convex surface; irradiating the concave and convex surface of the manufactured substrate with inspection light from a direction oblique to a normal direction and detecting returning light of the inspection light returned from the concave and convex surface by a light-receiving element provided in the normal direction of the concave and convex surface; and judging unevenness of luminance of the concave and convex surface by an image processing device based on light intensity of the returning light received. An organic EL element which includes a diffraction-grating substrate having an irregular concave and convex surface is produced with a high throughput.

Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.

Abstract: An organic layer deposition apparatus includes: a conveyer unit including a transfer unit, a first conveyer unit, and a second conveyer unit; a loading unit for fixing a substrate to the transfer unit; a deposition unit including a chamber and at least one organic layer deposition assembly; and a measuring unit located between the loading unit and the deposition unit to measure position information of the substrate before an organic layer is deposited onto the substrate; and an unloading unit for separating, from the transfer unit, the substrate onto which the deposition has been completed, wherein the transfer unit is configured to cyclically move between the first conveyer unit and the second conveyer unit, and wherein the substrate fixed to the transfer unit is configured to be spaced apart from the at least one organic layer deposition assembly while being transferred by the first conveyer unit.

Abstract: An extended preform of a thermal interface material (TIM) is formed between a heat spreader and a die on a substrate. The preform has an extension beyond a footprint of the die. The preform is cured. A bleed out of the TIM is controlled by the extension upon curing of the preform.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor.

Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.

Abstract: A method of orienting a semiconductor wafer. The method includes rotating a wafer about a central axis; exposing a plurality of edge portions of the rotating wafer to light having a predetermined wavelength from one or more light sources; detecting a subsurface mark in one of the plurality of edge portions of the rotating wafer; and orienting the wafer using the detected subsurface mark as a reference.

Abstract: A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: According to the invention, a monitoring device (12) is created for monitoring a thinning of at least one semiconductor wafer (4) in a wet etching unit (5), wherein the monitoring device (12) comprises a light source (14), which is designed to emit coherent light of a light wave band for which the semiconductor wafer (4) is optically transparent. The monitoring device (12) further comprises a measuring head (13), which is arranged contact-free with respect to a surface of the semiconductor wafer (4) to be etched, wherein the measuring head (13) is designed to irradiate the semiconductor wafer (4) with the coherent light of the light wave band and to receive radiation (16) reflected by the semiconductor wafer (4). Moreover, the monitoring device (12) comprises a spectrometer (17) and a beam splitter, via which the coherent light of the light wave band is directed to the measuring head (13) and the reflected radiation is directed to the spectrometer (17).

Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.

Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

Abstract: Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.

Abstract: A wafer level image module includes a photo sensor for outputting an electrical signal upon receiving light, a lens set for focusing incident light onto the photo sensor, and an adjustment member disposed between the photo sensor and the lens set for controlling the distance between the photo sensor and the lens set to compensate the focus offset of the photo sensor for enabling the lens set to accurately focus the incident light onto the photo sensor in an in-focus manner so as to provide a high image quality.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Abstract: A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit.

Abstract: In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump.

Abstract: A method is provided for assembling a stack of surface-mount devices (SMDs) on a substrate. The method provides a substrate, die, or printed circuit board (PCB) with a top surface having a landing pad and a first reference feature. An alignment jig is placed overlying the substrate top surface. The alignment jig second reference feature is aligned with respect to the substrate first reference feature. A first SMD is placed overlying the substrate landing pad. The first SMD third reference feature is aligned with respect to the alignment jig second reference feature. A second SMD is placed overlying the substrate top surface. Then, the alignment jig first boundary feature is mated with the second SMD second boundary feature. In response to the mating, the second SMD first interface is aligned over an underlying SMD active element.

Abstract: A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator.

Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.

Abstract: A method of manufacturing a solar cell including providing a substrate, depositing a first electrode over the substrate and depositing at least one p-type semiconductor absorber layer over the first electrode. The p-type semiconductor absorber layer comprises a copper indium selenide (CIS) based alloy material. The method also includes depositing by reactive sputtering an n-type In-VI semiconductor layer over the at least one p-type semiconductor absorber layer and depositing a second electrode over the n-type In-VI semiconductor layer.

Abstract: An image pickup section picks up images of a pair of targets formed on a substrate with a cutting line interposed therebetween (S101). An extracting section extracts the targets from the images (S102). Then, a measuring section measures the distance d1 between the targets (S103). When a driving section presses a blade against the substrate (S104), the substrate is pressed by the blade to become warped and starts to break. Thus, the image pickup section picks up images of the targets again (S105), and the extracting section extracts the targets from the images (S106). The measuring section measures the distance d2 between the targets (S107). A determining section determines the cutting state of the substrate from the amount of change (d2?d1) of the distances between the targets (S108).