Abstract: The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases.

Abstract: There is testing of individual dice prior to their inclusion in a multi-chip package. A wafer is sawn into individual dice and the dice are placed onto a die tray. If the tray is not full, then dice can be added that originate from other wafers. Contacts perform diagnostic tests upon the dice to determine if individual dice function as expected. Mapping talkes place to distinguish between dice that passed the diagnostic test and those that did not. Multiple tests can take place in series, where various forms of consolidation and mapping takes place. Passing dice can become part of a multi-chip package while failing dice can be re-screened or scrapped.

Abstract: The present invention provides a recovery processing method to restore the substrate processing apparatus to an operating state after correcting an abnormality having occurred in the substrate processing apparatus in operation and having resulted in a stop in the operation, comprising a substrate retrieval step in which substrate salvage processing is first executed for a wafer W left in a chamber in the substrate processing apparatus in correspondence to the extent to which the wafer has been processed at the time of the operation stop and the substrate having undergone the substrate salvage processing is then retrieved into the cassette storage container and an apparatus internal state restoration step in which the states inside the individual chambers of the substrate processing apparatus are restored.

Abstract: An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die.

Abstract: When a multi-layer structure is formed by forming the interconnect trenches or via holes having different patterns in a plurality of insulating films, an anti-reflective film and an upper resist film are stacked in this order over an insulating interlayer, and the anti-reflective film is etched through the upper resist film used as a mask, wherein the anti-reflective film is etched while varying a value of at least one etching condition correlative to ?(L2?L1), expressing dimensional shift of width L2 of opening of the recess formed in the insulating film, with respect to width L1 of opening of the upper resist film, so as to reduce the dimensional shift ?(L2?L1) as the aperture ratio of the opening to be formed in the upper resist film increases, depending on the aperture ratio.

Abstract: A test structure for inspecting an allowable process margin in a manufacturing process for a semiconductor device is provided. The test structure includes a plurality of grounded conductive lines on a substrate and electrically grounded to the substrate. A plurality of floating conductive lines are provided, each of the plurality of conductive lines being spaced apart from the grounded conductive lines and electrically separated from the grounded conductive lines on the substrate. A plurality of supplementary patterns are provided for measuring the allowable process margin by a voltage contrast between the grounded conductive lines and the floating conductive lines. Related methods of testing are also provided.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: An apparatus that performs electrical testing is described. This apparatus includes a first semiconductor die that is to be tested, and a connector configured to be coupled to a first surface of the first semiconductor die. Furthermore, a thermal interface in the apparatus is between a second surface of the first semiconductor die and a heat-removal device. This thermal interface includes a metal which is in a liquid state at an operating temperature of the semiconductor die during the testing.

Abstract: One embodiment of the present invention includes a method for aligning a wafermap with a semiconductor wafer. The method may comprise assigning a location code to each of a plurality of dies on the wafermap. Each of the plurality of dies on the wafermap can correspond to each of a plurality of dies on the semiconductor wafer. The method may also comprise scanning an approximate location of a reference die on the semiconductor wafer with a die detection sensor based on the location code corresponding to a location of the reference die on the wafermap and determining a physical location of the reference die on the semiconductor wafer using the die detection sensor. The method may further comprise correlating the physical location of the reference die on the semiconductor wafer with the respective location code corresponding to the reference die on the wafermap.

Abstract: A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

Abstract: A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.

Abstract: Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.

Abstract: A method of indicating the progress of a sacrificial material removal process, the method, comprising; freeing a portion of a member, the member being disposed in a cage and laterally surrounded by the sacrificial material; and preventing the freed portion of the member from floating away by retaining the freed member.

Abstract: Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

Abstract: A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surface of the semiconductor substrate. The method further includes re-measuring the thickness of the insulating film to determine etch rates for the film at selected locations on the surface of the semiconductor wafer, and based on the determined etch rates, determining misalignment of the semiconductor wafer.

Abstract: Systems and methods are disclosed for producing vertical LED array on a metal substrate; evaluating said array of LEDs for defects; destroying one or more defective LEDs; forming good LEDs only LED array suitable for wafer level package.

Abstract: An integrated circuit structure has an IC chip, at least a functional bump, and at least a dummy bump positioned on a joint surface of the IC chip. A terminal surface of the dummy bump is different in appearance from a terminal surface of the functional bump, which improves an inspection process during production of the IC chip.

Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.

Abstract: A method of improving a semiconductor substrate including a SiGe film on a Si or SOI substrate is provided. The method includes determining a relationship between a film condition of the SiGe film and a hydrogen ion implantation condition used in making the SiGe film so as to achieve relaxation of lattice distortion in the SiGe film as well as improved crystallinity and/or surface condition of the SiGe film, so that improved conditions for improving quality of the SiGe film on the Si or SOI substrate can be determined.

Abstract: The invention is directed to a method for adjusting sizes and shapes of plug openings for border plug openings overlapping with trenches respectively, wherein the border plug openings are separated from each other with a distance equal to or smaller than a specific distance. The method comprises performing an adjusting process for separating the border plug openings away from each other and enlarging the dimensions of the border plug openings so that the border plug openings are located within the trenches respectively and the edges of the borer openings are separated from the sidewalks of the trenches, wherein the border plug openings are enlarged within ranges of the trenches respectively.

Abstract: A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a direct-writing tool; forming a photoresist layer on the semiconductor wafer; locally exposing the photoresist layer within the defective regions using an energy beam; developing the photoresist layer on the semiconductor wafer; and wafer-processing the semiconductor wafer under the photoresist layer after exposing and developing.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation.

Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.

Abstract: Methods for transferring substrates in a system with a factory interface robot between at least one FOUP, a buffer coupled to a parasitic device and an inbound and outbound transfer station coupled to a processing tool are provided. In one embodiment, a method for transferring substrates includes transferring a first substrate on an end effector of a robot from a FOUP to a buffer station serving a parasitic device, moving the substrate from the buffer station into the parasitic device, picking up a second substrate on the end effector, compensating for a residence time of the first substrate in the parasitic device, transferring the second substrate to parasitic device from the end effector to the buffer station serving the parasitic device, and picking up the first substrate from the buffer station.

Abstract: A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.

Abstract: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.

Abstract: A substrate (1) is formed from a non-electrically conducting material and is for mounting a semiconductor chip (10). The substrate has a semiconductor chip mounting portion (6). A number of first electrically conducting contact portions (5) are formed on the surface of the material and associated with the mounting portion (6). A second electrically conducting contact portion (3) is formed on the surface of the material, and the second electrically conducting contact portion (3) is adapted to be coupled to testing equipment. A number of electrically conducting paths (4) are formed on the surface of the material. The conducting paths (4) electrically connect the second electrically conducting contact portion (3) to a minority of the first electrically conducting contact portions (5).

Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Abstract: The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at least one characteristic parameter associated with at least one device structure on the at least one workpiece. The method also includes comparing the at least one characteristic parameter associated with the at least one non-device structure and the at least one characteristic parameter associated with at least one device structure.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is made whether the ion implantation is within acceptable tolerance(s).

Abstract: Disclosed is a method for measuring a low-k material. A surface of the low-k material is changed into oxide by an oxygen plasma used in an ashing process (e.g., to remove a photoresist film after an etching process). A thickness of the low-k material is measured using an optical measurement system, and then the low-k material is treated with plasma in an ashing process to change the surface of the low-k material into oxide. The substrate is wet-cleaned with an inorganic or organic cleaning solution after the ashing process to remove the surface oxide. Then, a subsequent thickness of the low-k material is measured using the optical measurement system, and a thickness of the oxide is calculated by comparing the measured values. The thickness of a damaged low-k material is thereby measured in an easy and rapid manner since optical measurement system typically installed in the semiconductor fabrication facility (fab) is utilized.

Abstract: A method for manufacturing a semiconductor device with plural semiconductor chips is provided. The method includes the step of attaching a second semiconductor chip to a first surface of a supporting member in a manner such that a third set of electrodes are wirelessly connected to the supporting member at positions outwardly from an opening of the supporting member. The method also includes the step of mounting a first semiconductor chip to the second semiconductor chip in a manner such that the main surfaces of the first and second semiconductor chips face each other while a first set of electrodes of the first semiconductor chip are wirelessly connected to a second set of electrodes in the opening of the supporting member.

Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Abstract: A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or “bins” according to the measured parameters. Measurable parameters include performance/speed-grading, power consumption, current leakage, and the ability to operate at certain temperature extremes. A method for speed grading semi-custom ASIC devices is specifically described that does not require removing partially completed wafers from the fab line for testing. To speed-grade a new boat of partially completed un-customized wafers, a small number of wafers (1 or 2) are processed to completion while being customized specifically for a customer design requiring only the slowest bin. These wafer(s) are then performance tested and the remaining wafers in the boat are certified according to these results for their performance level and placed in a wafer bank for later use.

Abstract: In a method of aligning a wafer, which is capable of precisely and rapidly aligning the wafer, and a wafer alignment apparatus using the method of aligning the wafer, a first wafer is aligned to form a first template pattern corresponding to an image of the first wafer. Image data of a second wafer is inputted. A kind of the second wafer is different from that of the first wafer. A second template pattern is formed by transforming the first template pattern in response to the image data of the second wafer. The second wafer is then aligned in response to the second template pattern. Accordingly, the template pattern is formed using the image data to align the wafer although wafers having different images are inspected, thereby rapidly forming the template pattern.

Abstract: Automated defect sourcing system identifies root-causes of yield excursion due to contamination, process faults, equipment failure and/or handling in timely manner and provides accurate timely feedback to address and contain the sources of yield excursion. A signature bank stores known wafer surface manufacturing defects as defect signatures. The signature of a manufacturing defect pattern is associated with a type of equipment or process, and used to source the manufacturing defects and to provide process control for changing and/or stopping yield excursion during fabrication. A defect signature recognition engine matches wafer defects against the signature bank during wafer fabrication. Once the defect signature is detected during fabrication, handling and/or disposing the root-cause of the corresponding defect is facilitated using messages according to an event handling database. Optionally, a real-time process control for wafer fabrication is provided.

Abstract: The invention relates to a method for enabling repair of a defect in a substrate, particularly the invention provides a method and apparatus for enabling repair of a pattern shape in a semiconductor device, which has not been able to be practiced because of lack of a suitable method, and further provides a method for manufacturing the semiconductor device using those. A method for repairing the pattern shape of a substrate having an imperfect pattern is used, which includes (a) a step for inspecting the substrate and thus detecting the imperfect pattern, and (b) a step for repairing the pattern shape by performing etching or deposition to the detected imperfect-pattern using radiation rays. Moreover, apparatus for repairing a pattern shape of a via-hole in a wafer having an imperfect via-hole is used, which has a defect inspection section for detecting the imperfect via-hole, and an etching section for etching the imperfect via-hole using a fast atom beam.

Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.

Abstract: Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

Abstract: Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure. Far each localized defect, the same charged particle beam based tool may then be used to generate a high resolution image of the localized defect whereby the high resolution image can later be used to classify the each defect. In one embodiment, the defect's presence and location are determined without rotating the test structure relative to the charged particle beam.

Abstract: A method for manufacturing a semiconductor device includes, (a) mounting a plurality of first semiconductor chips in a manner not to overlap with one another on a substrate having a plurality of wiring patterns formed thereon, and electrically connecting each of the first semiconductor chips to any one of the wiring patterns, (b) conducting an electrical examination on a plurality of mounted bodies each including one of the first semiconductor chips and any one of the wiring patterns electrically connected to each other, (c) stacking a second semiconductor chip on the first semiconductor chip of any one of the mounted bodies that pass the electrical examination, excluding any of the mounted bodies that fail the electrical examination and thereafter, (d) cutting the substrate so as to divide the wiring patterns.

Abstract: One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.

Abstract: A method of increasing the cell retention capacity of a silicon nitride read-only-memory on a wafer. The method includes carrying out a baking process after performing the last plasma treatment of the wafer but before a wafer sort test.

Abstract: A semiconductor process and yield analysis integrated real-time management method comprises inspecting a plurality of semiconductor products with a plurality of items to generate and record a plurality of inspecting results during semiconductor process, classifying the semiconductor products as a plurality of groups with a default rule to generate and record an initial data in a database, indexing a plurality of semiconductor product groups and the corresponding initial data from the database by a default product rule and parameter to calculate a corresponding analysis result, and displaying the analysis result according to the indexed semiconductor product groups and the initial data.

Abstract: A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. In the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the chips on a wafer is controlled based on a chip identification information formed on a wafer. The method includes the step of editing the chip identification information such that the chip identification information for chips having the same fabrication processing steps and chips formed on the same wafer can be read out successively. The method also includes the step of carrying out each of the fabrication processing steps based on the chip identification information formed on the wafer by reading out the chip identification information.

Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are moveable among them and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.

Abstract: A measuring method of the contact resistance of a probe includes bringing a plurality of probes including a first and second probes into contact with a plurality of electrode pads that is disposed on a semiconductor device to be electrically tested and connected each other with a conductive wiring; connecting a power supply to at least one predetermined first probe of the plurality of probes and supplying a current or a voltage from the first probe through the electrode pad and the wiring to the second probe to the semiconductor device; measuring the contact resistance between the electrode pad and the probe based on the current or the voltage supplied to the semiconductor device; judging whether the measured contact resistance is equal to or more than a predetermined value or not; and when the contact resistance is equal to or more than the predetermined value, the probes are cleansed.

Abstract: The present invention is generally directed to fault detection and control methodologies for ion implant processes, and a system for performing same. In one illustrative embodiment, the method comprises performing a tuning process for an ion implant tool, the tuning process resulting in at least one tool parameter for the ion implant tool, selecting or creating a fault detection model for an ion implant process to be performed in the ion implant tool based upon the tool parameter resulting from the tuning process, and monitoring an ion implant process performed in the ion implant tool using the selected or created fault detection model.