Abstract: A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.

Abstract: A method and apparatus for correcting overlay errors in a lithography system. During lithographic exposure, features being exposed on the wafer need to overlay existing features on the wafer. Overlay is a critical performance parameter of lithography tools. The wafer is locally heated during exposure. Thermal expansion causes stress between the wafer and the wafer table, which will cause the wafer to slip if it exceeds the local frictional force. To increase the amount of expansion allowed before slipping occurs, the wafer chuck is uniformly expanded after the wafer has been loaded. This creates an initial stress between the wafer and the wafer table. As the wafer expands due to heating during exposure, the expansion first acts to relieve the initial stress before causing an opposite stress from thermal expansion. The wafer may be also be heated prior to attachment to the wafer chuck, creating the initial stress as the wafer cools.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.

Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitoring system, generating first and second sequences of values from the first and second sequences of measured spectra, fitting first and second linear functions to the first and second sequences of values, determining a difference between the first linear function and the second linear function, adjusting at least one parameter of a second set of parameters based on the difference, and polishing the substrate on a second platen using the adjusted parameter.

Abstract: A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation film; a wiring pattern and a frame-shaped wiring dummy pattern formed on the underlying insulation film; and plural insulation films formed on the upper side of the underlying insulation film, the wiring pattern, and the wiring dummy pattern. At least one SOG film is included in the plural insulation films, in which a color pattern in accordance with a distance from the center of the semiconductor wafer based on the SOG film is formed on a surface of the insulator film within the wiring dummy pattern in top view.

Abstract: A compact multiple diameter wafer testing device with a footprint of about 33 by 34 inches features on-chuck wafer calibration and integrated cassette-chuck transfer. It includes a five axes wafer handling system, a quick exchange chuck and a fixed through beam sensor fixed. Two of the five axes are provided by an X-Y stage, a third axis is provided by a rotary stage on top of the X-Y stage, a fourth axis belongs to a rotating effector and a fifth axis is provided by motion controlled pin lifters all combined with the X-Y stage. The quick exchange chuck may be easily changed for different wafer diameters and also calibrated by the through beam sensor. The through beam sensor provides on-chuck position calibration of the chucked wafers in conjunction with the X-Y stage and rotary stage. The compact wafer testing device handles wafers between six and twelve inches diameter.

Abstract: A method of monitoring a processing system for processing a substrate during the course of semiconductor manufacturing is described. The method comprises acquiring data from the processing system for a plurality of observations. It further comprises constructing a principal components analysis (PCA) model from the data, wherein a weighting factor is applied to at least one of the data variables in the acquired data. The PCA mode is utilized in conjunction with the acquisition of additional data, and at least one statistical quantity is determined for each additional observation. Upon setting a control limit for the processing system, the at least one statistical quantity is compared with the control limit for each additional observation. When, for example, the at least one statistical quantity exceeds the control limit, a fault for the processing system is detected.

Abstract: A retuning process particularly useful with an Ar/H2 smoothing anneal by rapid thermal processing (RTP) of a silicon-on-insulator (SOI) wafer performed after cleavage. The smoothing anneal or other process is optimized including a radial temperature profile accounting for the edge ring and exclusion zone and the vertically structured SOI stack or other wafer gross structure. The optimized smoothing conditions are used to oxidize a bare silicon wafer and a reference thickness profile obtained from it is archived. After extended processing of complexly patterned production wafers, another bare wafer is oxidized and its monitor profile is compared to the reference profile, and the production process is adjusted accordingly. In another aspect, a jet of cooling gas is preferentially directed to the edge ring and peripheral portions of the supported SOI wafer to cool them relative to the inner wafer portions.

Abstract: A method is provided for controlling a dose amount of dopant to be doped into an object to be processed in plasma doping. According to the method, the doping control is formed of the following processes: determining the temperature of the object, the amount of ions having dopant in plasma that collide with the object, and types of gases in plasma during doping; calculating a dose amount by neutral gas according to the temperature of the object, and a dose amount by ions from the determined amount of ions containing dopant that collide with the object; and carrying out doping so that the sum of the dose amount by neutral gas and the dose amount by ions equal to a predetermined dose amount.

Abstract: A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second semiconductor chip, and the first marks and the second marks are different from each other in at least either one of size and geometry.

Abstract: A method of monitoring a heat treatment of a microtechnological substrate includes placement of the substrate to be treated in a heating zone and applying a heat treatment to the substrate, under predetermined temperature conditions, while monitoring the change over the course of time in the vibratory state of the substrate, and detecting a fracture in the substrate by detecting a peak characteristic in the vibratory state over the course of time.

Abstract: Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.

Abstract: Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.

Abstract: By using powerful data analysis techniques, such as PCR, PLS, CLS and the like, in combination with measurement techniques providing structural information, gradually varying material characteristics may be determined during semiconductor fabrication, thereby also enabling the monitoring of complex manufacturing sequences. For instance, the material characteristics of sensitive dielectric materials, such as ULK material, may be detected, for instance with respect to an extension of a damage zone, in order to monitor the quality of metallization systems of sophisticated semiconductor devices. The inline measurement data may be obtained on the basis of infrared spectroscopy, for instance using FTIR and the like, which may even allow directly obtaining the measurement data at process chambers, substantially without affecting the overall process throughput.

Abstract: A semiconductor laser device manufacturing method includes, sequentially, a first aging step S1, a first inspection step S2, a mounting step S3, a second aging step S4 and a second inspection step S5. Since the first aging step S1 on a semiconductor laser chip with a high-temperature direct current conduction is performed before the mounting step S3, threshold current and drive current of the semiconductor laser chip before mounting can be reduced.

Abstract: A chip package including a substrate, a chip and a mark is provided. The substrate has a carrying surface. A mark region is disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the substrate. The mark is disposed in the mark region for recording a process parameter.

Abstract: A method of etching a semiconductor wafer is provided. The method comprises the steps of: jetting a mixed gas including hydrogen fluoride and ozone onto a surface of a semiconductor wafer; monitoring the surface of the semiconductor wafer; analyzing the surface of the semiconductor wafer; and adjusting at least one of the hydrogen fluoride concentration and the ozone concentration in the mixed gas based on a result of the analysis.

Abstract: A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a first polishing process of removing the metal film, after the first polishing process, performing a second polishing process of removing the barrier film, after the second polishing process, performing a third polishing process of polishing the insulating film, during the second polishing process and the third polishing process, monitoring a polishing state of the substrate with an eddy current sensor, and terminating the third polishing process when an output signal of the eddy current sensor reaches a predetermined threshold.

Abstract: A product information marking method including a back side grinding step for grinding the back side of a wafer having a plurality of devices formed on the front side so as to be partitioned by a plurality of separation lines, thereby obtaining a desired thickness of the wafer. After performing the back side grinding step, a marking step for marking product information on the back side of each device by applying a laser beam to the back side of the wafer is performed before separating the devices from each other. Thus, the product information is marked on each device in the stage of the wafer.

Abstract: A semiconductor substrate having a reference semiconductor chip and a method of assembling semiconductor chips using the same are provided. According to the method, a semiconductor substrate having a plurality of semiconductor chips is provided. An identification mark is made on a reference semiconductor chip among the semiconductor chips. The semiconductor substrate is aligned with reference to the reference semiconductor chip, so that an electrical die sorting test can be performed on the semiconductor chips on the semiconductor substrate.

Abstract: A position aligning apparatus performs position alignment of a pattern in a current process of a pattern exposure process by using a pattern formed before the current process. The position aligning apparatus includes: a correction calculating section configured to calculate a correction value set of a current lot about each of misalignments in scale and rotation of a pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets in the immediately-preceding lot to a process immediately-preceding to the current process, and a summation of completeness value sets in the current lot to the immediately-preceding process; and a correction control unit configured to control correction of the scale and the rotation of the pattern in the chip by using the correction value sets.

Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.

Abstract: A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of wafers to be processed.

Abstract: An etching process state judgment method comprising: a spectral data obtaining step, in which an optical emission spectrum distribution is obtained by monitoring optical emission during an etching process of a plurality of wafers; a peak detection step, in which peaks are detected from the optical emission spectrum distribution at a specific time point during the etching process, to obtain peak characteristics; a common peak identifying step, in which peaks common to the wafers are identified among the peaks detected in the peak detection step; and a state detection step, in which the characteristics are compared regarding the common peaks, to detect a state of each wafer in the etching process. A state (anomaly or normalcy) of an etching process is detected from optical emission spectrum distribution at the time of etching process, by a simple method without assuming substances.

Abstract: Embodiments of controlling a fabrication process using an iso-dense bias are generally described herein. Other embodiments may be described and claimed.

Abstract: The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.

Abstract: Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

Abstract: A method is provided, of manufacturing a material to be etched that can more preferably prevent a region to be etched from remaining as an un-etched region and reduce deviation of etched/un-etched regions. Patterning (a method of manufacturing a material to be etched) of a substrate 100, which is manufactured by performing etching through an opened region 10 by an etching mask M1, is performed by a first etching process and a second etching process that is performed after the first etching process. The second etching process is a process for etching a region including a region that is not etched by the first etching process. An un-etched region, which is the same as etched using a virtual etching mask M1?, is formed on the surface of an object to be etched by the first and second etching processes.

Abstract: A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326.

Abstract: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step, a continuity test is performed by pressing bumps 21 against the contacts 2. In a final third step, the contacts 2 pressed are melted to connect the connecting terminals 12 to the bumps 21. That is, the semiconductor chip 20 is connected to the mounting circuit 10 while maintaining a state in which they pass the continuity test, thereby significantly reducing the occurrence of defective continuity in the semiconductor-chip-mounting circuit 1.

Abstract: Novel methods and apparatuses for annealing semiconductor devices in a high pressure gas environment. According to an embodiment, the annealing vessel has a dual chamber structure, and potentially toxic, flammable, or otherwise reactive gas is confined in an inner chamber which is protected by pressures of inert gas contained in the outer chamber. The incoming gas delivery system and exhaust gas venting system are likewise protected by various methods. Embodiments of the present invention can be used, for example, for high-K gate dielectric anneal, post metallization sintering anneal, and forming gas anneal in the semiconductor manufacturing process.

Abstract: A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern.

Abstract: To prevent breakage of a membrane probe during a probe test using a probe card having the membrane probe, appearance of a main surface of a wafer as a test object is tested by an appearance tester 51, and results of bad appearance such as adhesion of a foreign substance to the main surface of the wafer and abnormality in shape of bump electrodes over the main surface of the wafer are collected as wafer map data according to arrangement of respective chips in a plane of the wafer, then the wafer map data are transmitted to a probe tester 53 via a server 52, and the probe tester 53 omits the probe test for chips in which bad appearance was detected, and concurrently performs the probe test to other chips in which bad appearance was not detected, based on the wafer map data.

Abstract: A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.

Abstract: A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.

Abstract: The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases.

Abstract: Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize defects on the test chip.

Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.

Abstract: A method for analyzing the warpage of organic laminates used in flip chip packages includes collecting warpage data and layer thickness data for several laminates. A principal components analysis may then be performed on the thickness data to calculate orthogonal basis vectors to re-express the thickness data in a different basis. The thickness data may then be projected onto the orthogonal basis vectors. A linear model may be generated that expresses the warpage data for each laminate in terms of the projection of corresponding thickness data onto the orthogonal basis vectors, each projection multiplied by a weight. These weights may then be analyzed to determine the contribution of each orthogonal basis vector to the variance of the warpage data. The contribution and structure of each orthogonal basis vector may then be interpreted to estimate the importance of each layer or combination of layers in contributing to the laminate warpage.

Abstract: A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting a gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel region of the TFT using the dual or multiple gates in the case where Gs, the size of crystal grains of polycrystalline silicon forming a TFT substrate, ? angle in which “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the gates, the width of the active channels and the length of the active channels are determined.

Abstract: In embodiments, a method for manufacturing a semiconductor device may include forming a diffusion preventing layer on a semiconductor substrate having a conductive layer, forming an intermetallic insulating layer on the diffusion preventing layer, forming a trench photo resist layer formed above the intermetallic insulating layer of a first photo resist material, forming a via hole photo resist layer of a second photo resist material at an upper portion and a sidewall in a contact hole of the trench photo resist layer, etching the intermetallic insulating layer and the diffusion preventing layer using the via hole photo resist layer and the trench photo resist layer to substantially simultaneously form a via hole and a trench, and filling the via hole and the trench with a metal thin film to form a metal line.

Abstract: In a disclosed good chip classifying method capable of classifying the good chips on a wafer, defective chips are divided into defective groups so that the defective chips contiguous to each other are placed into the same defective group based on the wafer test results; the defective group is judged as a defective chip concentrated distribution area when the number of the defective chips exceeds the prescribed value; a defective chip concentrated distribution nearby area including all the defective chips in the defective chip concentrated distribution area and nearby good chips is formed; and the good chips in the defective chip concentrated distribution nearby area are classified to have a chip index based on four directions (X and Y axis directions) on which the defective chips in the defective chip concentrated distribution area are disposed.

Abstract: A method of making a semiconductor thin film bonded to a handle substrate includes implanting a semiconductor substrate with a light ion species while cooling the semiconductor substrate, bonding the implanted semiconductor substrate to the handle substrate to form a bonded structure, and annealing the bonded structure, such that the semiconductor thin film is transferred from the semiconductor substrate to the handle substrate.

Abstract: By providing an under-specified specification for designating a destination carrier in a respective control job or control message, a high degree of flexibility in determining the destination of processed substrates may be obtained, thereby also allowing the removal of a source carrier for enhancing load port availability in complex semiconductor facilities.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.