Abstract: An apparatus for dispensing fluid during semiconductor substrate processing operations comprises an enclosure having a first side and a second side. The enclosure comprises a first processing station and a second processing station. The second processing station is positioned adjacent to the first processing station. In addition, the substrate processing apparatus includes a first dispense arm configured to deliver a fluid to the first processing station wherein the first dispense arm is positioned between the first side and the first processing station and a second dispense arm configured to deliver the fluid to the second processing station wherein the second dispense arm is positioned between the second side and the second processing station. The substrate processing apparatus also comprises a first rinse arm configured to deliver a rinsing fluid to the first processing station and a second rinse arm configured to deliver the rinsing fluid to the second processing station.

Abstract: Systems, methods and apparatus for regulating ion energies in a plasma chamber and chucking a substrate to a substrate support are disclosed. An exemplary method includes placing a substrate in a plasma chamber, forming a plasma in the plasma chamber, controllably switching power to the substrate so as to apply a periodic voltage function to the substrate, and modulating, over multiple cycles of the periodic voltage function, the periodic voltage function responsive to a desired distribution of energies of ions at the surface of the substrate so as to effectuate the desired distribution of ion energies on a time-averaged basis.

Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.

Abstract: A method is provided, of manufacturing a material to be etched that can more preferably prevent a region to be etched from remaining as an un-etched region and reduce deviation of etched/un-etched regions. Patterning (a method of manufacturing a material to be etched) of a substrate 100, which is manufactured by performing etching through an opened region 10 by an etching mask M1, is performed by a first etching process and a second etching process that is performed after the first etching process. The second etching process is a process for etching a region including a region that is not etched by the first etching process. An un-etched region, which is the same as etched using a virtual etching mask M1?, is formed on the surface of an object to be etched by the first and second etching processes.

Abstract: A method of controlling the polishing of a substrate includes polishing a substrate on a first platen using a first set of parameters, obtaining first and second sequences of measured spectra from first and second regions of the substrate with an in-situ optical monitoring system, generating first and second sequences of values from the first and second sequences of measured spectra, fitting first and second linear functions to the first and second sequences of values, determining a difference between the first linear function and the second linear function, adjusting at least one parameter of a second set of parameters based on the difference, and polishing the substrate on a second platen using the adjusted parameter.

Abstract: The present invention relates to a method for inspecting a light-emitting device, the method including performing a light emission test of (A) a light-emitting device including a lead frame having mounted and packaged thereon a plurality of light-emitting elements or (B) a light-emitting device obtained by resin encapsulating and packaging the light-emitting device (A), by applying a current to the plurality of light-emitting elements and judging each light-emitting element as passed or failed, in which arrangement of the plurality of light-emitting elements in the light-emitting device is set as in the following (?): (?) In a lead frame having a lattice form including a plurality of rows and a plurality of columns with a plurality of intersection points formed thereby, a plurality of light-emitting elements are disposed between the adjacent intersection points in each row, the adjacent light-emitting elements in each row are connected to each other so that positive electrode terminals or negative electrode t

Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Abstract: Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

Abstract: A method of fabricating light emitting diode chips having a phosphor coating layer comprises providing a substrate having a plurality of light emitting diodes formed thereon; forming a conductive bump on at least one of the plurality of light emitting diodes; forming a phosphor coating layer over the substrate and the light emitting diodes; cutting the phosphor coating layer by a point cutter to remove an upper portion of the phosphor coating layer, so as to reduce a thickness of the phosphor coating layer and expose the conductive bump; and forming a plurality of individual light emitting diode chips having the phosphor coating layer by separating the plurality of light emitting diodes.

Abstract: Various embodiments of methods and systems for designing and constructing displays from multiple light-modulating elements are disclosed. Display elements having different light-modulating and self-assembling characteristics may be used during display assembly and operation.

Abstract: Disclosed is a substrate processing apparatus including: a substrate processing unit that performs substrate processing by supplying a processing liquid to a substrate to be processed; a positioning mechanism that contacts the sides of the substrate to determine the position of the substrate; a positioning driver that drives the positioning mechanism; a detector that detects the position of the positioning mechanism; a storage unit that stores the position of the positioning mechanism with respect to a reference substrate serving as a reference of the substrate as a reference position information; and an operator that calculates a difference between the reference position information and the position information of the positioning mechanism detected in the detector and calculates measurement information on the processed substrate based on the difference.

Abstract: In a method of manufacturing a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), an epitaxial layer may be formed on a first substrate including a chip area and a scribe lane area. A first impurity layer may be formed adjacent to the first substrate by implanting first impurities into the epitaxial layer. A photodiode may be formed in the epitaxial layer on the chip area. A circuit element electrically connected to the photodiode may be formed on the epitaxial layer. A protective layer protecting the circuit element may be formed on the epitaxial layer. A second substrate may be attached onto the protective layer. The first substrate may be removed to expose the epitaxial layer. A color filter layer may be formed on the exposed epitaxial layer using the first impurity layer as an alignment key. A microlens may be formed over the color filter layer.

Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: A system and method for monitoring a manufacturing process of a fan-out wafer, the method may include acquiring a first set of images of dies after a completion of a first manufacturing stage of a manufacturing process of the fan-out wafer; processing the first set of images to detect defects; performing at least one corrective operation in response to at least one defect detected by processing the first set of images; acquiring a second set of images of dies after a completion of a second manufacturing stage of the manufacturing process of the fan-out wafer, the second manufacturing process follows the first manufacturing process; processing the second set of images to detect defects; and performing at least one corrective operation in response to at least one defect detected by processing the second set of images.

Abstract: An improved method for the fabrication of Micro-Electro-Mechanical Systems (MEMS), Nano-Electro-Mechanical Systems (NEMS), Photonics, Nanotechnology, 3-Dimensional Integration, Micro- and Nano-Fabricated Devices and Systems for both rapid prototyping development and manufacturing is disclosed. The method includes providing a plurality of different standardized and repeatable process modules usable in fabricating the devices and systems, defining a process sequence for fabricating a predefined one of the devices or systems, and identifying a series of the process modules that are usable in performing the defined process sequence and thus in fabricating the predefined device or system.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor.

Abstract: A method and system for non-invasive sensing and monitoring of a processing system employed in semiconductor manufacturing. The method allows for detecting and diagnosing drift and failures in the processing system and taking the appropriate correcting measures. The method includes positioning at least one non-invasive sensor on an outer surface of a system component of the processing system, where the at least one invasive sensor forms a wireless sensor network, acquiring a sensor signal from the at least one non-invasive sensor, where the sensor signal tracks a gradual or abrupt change in a processing state of the system component during flow of a process gas in contact with the system component, and extracting the sensor signal from the wireless sensor network to store and process the sensor signal. In one embodiment, the non-invasive sensor can be an accelerometer sensor and the wireless sensor network can be motes-based.

Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.

Abstract: Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.

Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.

Abstract: By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield loss compared to conventional strategies. The fault detection and classification mechanism may be advantageously applied to the electrochemical removal of underbump metallization layers during the formation of solder bump structures.

Abstract: A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key pattern of polysilicon in an active region of a semiconductor scribe lane.

Abstract: A management system includes a variable-period setting unit that sets a variable period in which quality-control values vary. Then, a retrieving unit retrieves events sandwiching the variable period. The events can be a maintenance of the semiconductor manufacturing device and/or a change of a correction value. An analysis-period setting unit sets an analysis period for analyzing a cause of variation of the quality-control values between the events retrieved by the retrieving unit.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a p-type impurity diffusion layer formed on the semiconductor substrate, and Ni silicide formed on the diffusion layer, wherein an alignment mark for lithography is formed on the Ni silicide.

Abstract: A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface of the insulating layer to bond the substrate having an insulating surface to the single crystal semiconductor substrate. Then, the single crystal semiconductor substrate is separated at the damaged region by performing heat treatment to form a single crystal semiconductor layer over the substrate having an insulating surface, and the single crystal semiconductor layer is patterned to form a plurality of island-shaped semiconductor layers. One of the island-shaped semiconductor layers is irradiated with a laser beam which is shaped to entirely cover the island-shaped semiconductor layer.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A method of manufacturing a light emitting device is provided in which satisfactory image display can be performed by the investigation and repair of short circuits in defect portions of light emitting elements. A backward direction electric current flows in the defect portions if a reverse bias voltage is applied to the light emitting elements having the defect portions. Emission of light which occurred from the backward direction electric current flow is measured by using an emission microscope, specifying the position of the defect portions, and short circuit locations can be repaired by irradiating a laser to the defect portions, turning them into insulators.

Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.

Abstract: Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster.

Abstract: Disclosed is an apparatus and method for plasma processing, which facilitates to constantly control a RF voltage supplied to a substrate supporting member by precisely detecting an inductive RF voltage induced to the substrate supporting member for a plasma, the apparatus comprising: a substrate supporting member for supporting a substrate, installed in a reaction room of a processing chamber; a RF generator for supplying a RF voltage to the substrate supporting member so as to form plasma in the reaction room; and a matching device for matching impedance of the RF voltage to be supplied to the substrate supporting member from the RF generator, wherein the matching device comprises: a matching unit for matching the impedance of RF voltage; and an inductive RF detecting unit which an inductive RF detecting voltage by removing noise frequency elements except a waveform of the RF voltage from a waveform of an inductive RF voltage induced to the substrate supporting member, and supplies the detected inductive RF

Abstract: An apparatus including a vacuum chamber having a substrate holding unit that holds a substrate and a plasma electrode facing the substrate, a first gas supply unit that supplies a H2 gas to the vacuum chamber at a constant flow rate, a second gas supply unit that opens or closes a valve to turn on or off the supply of a SiH4 gas, a high-frequency power source that applies a high frequency voltage to the plasma electrode, a shield box that is connected to a ground so as to surround the plasma electrode outside the vacuum chamber, and a control unit that controls the valve such that the SiH4 gas is periodically supplied to the vacuum chamber and modulates the amplitude of high frequency power in synchronization with the opening or closing of the valve, and the valve is provided in the shield box.

Abstract: Shapes and orientations of contacts or other closed contours on an integrated circuit are characterized by calculating Elliptic Fourier descriptors. The descriptors are then used for generating design rules for the integrated circuit and for assessing process capability for the manufacturing of the integrated circuit. Monte Carlo simulation can be performed in conjunction with the elliptic Fourier descriptors.

Abstract: Formation of a hybrid integrated circuit device is described. A design for the integrated circuit is obtained and separated into at least two portions responsive to component sizes. A first die is formed for a first portion of the hybrid integrated circuit device using at least in part a first minimum dimension lithography. A second die is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die has the second minimum dimension lithography as a smallest lithography used for the forming of the second die. The first die and the second die are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device.

Abstract: A method of manufacturing a semiconductor device according to an embodiment includes acquiring focus values measured for regions having different reflectance respectively due to films formed at a lower location than a resist formed above a semiconductor substrate, the focus values including a first focus value acquired at a first region of the regions having a lower reflectance and a second focus value acquired at a second region of the regions having a higher reflectance than the first region and bringing the second focus value closer to the first focus value, and carrying out an exposure processing.

Abstract: A test system and a failure parsing method. The test system may comprise a cell array including defective cells formed according to various failure causes, a test apparatus configured to measure electric characteristics from the defective cells and make the measured electric characteristics numerical, and a database apparatus configured to store the numerical electric characteristics. The failure parsing method may include forming defective cells to have at least one failure cause, measuring electric characteristics of each of the defective cells, storing the measured electric characteristics of each of the defective cells in a database, and judging failure causes of a failed chip of a semiconductor wafer based on the database.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: In a portion of a gate signal line and a portion of a common signal line, cutouts which are arranged perpendicular to the extending direction of these lines and open to face each other in an opposed manner are formed. A cruciform shape in appearance is formed by combining a gap defined between the gate signal line and the common signal line extending parallel to each other and the cutouts to each other. The cruciform portion formed in this manner is used as an alignment mark in the exposure of a photolithography step of a layer formed later. Due to such a constitution, in manufacturing a thin film transistor substrate, it is possible to realize the highly accurate alignment without forming a pattern only used for alignment.

Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).

Abstract: The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases.

Abstract: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized with a system for processing one or more substrates. The system may comprise an ion source for generating ions of desired species, the ions generated from the ion source being directed toward the one or more substrates along an ion beam path; a substrate support for supporting the one or more substrates; a mask disposed between the ion source and the substrate support, the mask comprising a finger defining one or more apertures through which a portion of the ions traveling along the ion beam path pass; and a first detector for detecting ions, the first detector being fixedly positioned relative to the one or more substrates.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: A chemical mechanical polishing apparatus including a platen for holding a pad having a polishing surface, a subsystem for holding a substrate and the polishing surface together during a polishing step, and a temperature sensor oriented to measure a temperature of the polishing surface, wherein the subsystem accepts the temperature measured by the sensor and is programmed to vary a polishing process parameter in response to the measured temperature. In an aspect, a chemical mechanical polishing apparatus having a platen for holding a pad having a polishing surface, a fluid delivery system for transporting a fluid from a source to the polishing surface, and a temperature controller which during operation controls the temperature of the fluid transported by the delivery system.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: In a substrate processing control method, a first process acquires a first-reflectance-spectrum of a beam reflected from the first-fine-structure and a second-reflectance-spectrum of a beam reflected from the second-fine-structure for each of varying-pattern-dimensions of the first-fine-structure when the pattern-dimension of the first-fine-structure is varied. A second process acquires reference-spectrum-data for each of the varying-pattern-dimensions of the first-fine-structure by overlapping the first-reflectance-spectrum with the second-reflectance-spectrum. A third process actually measures beams reflected from the first and the second-fine-structure, respectively, after irradiating light beam on to the substrate and acquiring reflectance-spectrums of the actual-measured beams as actual-measured spectrum data.

Abstract: In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of the gate; determining a gate length of a rectangular gate having electric characteristics equivalent to the calculated electric characteristics; calculating a corrective coefficient for describing an associated relationship between a statistical value of the extracted gate length distribution and the determined gate length; extracting a gate length distribution of a gate of a transistor by printing the design pattern, and calculating a gate length distribution representative value from the statistical value of the gate length distribution using the calculated corrective coefficient; and correcting the design pattern so that the calculated gate length distribution representative value will be a specification value.

Abstract: A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a second set of alignment edges. The alignment feature is inserted into the first aperture. The integrated circuit die is mechanically biased until the first and second set of alignment edges are in physical contact with one another and the alignment feature is secured into the mask window, thus forming an integrated circuit die assembly.

Abstract: There is provided a hybrid mounted device that includes a element such as semiconductor laser diode (LD), and a board such as a silicon platform having formed thereon an optical waveguide. The LD is mounted to the silicon platform, and is optically coupled to the optical waveguide. The mounting position of the LD is determined by positioning first alignment marks formed on the board and second alignment marks formed on the LD. In this configuration, initial positional deviation amount measuring marks that can measure the initial positional deviation amount of the first alignment marks themselves are formed on the board. The mounting position of the is corrected to a position where the second alignment marks are shifted with respect to the first alignment marks according to the initial positional deviation amount measured from the initial positional deviation amount measuring marks.

Abstract: A system and method for yield management is disclosed wherein a data set containing one or more prediction variable values and one or more response values is input into the system. The system can pre-process the input data set to remove prediction variables with missing values and data sets with missing values. The pre-processed data can then be used to generate a model that may be a decision tree. The system can accept user input to modify the generated model. Once the model is complete, one or more statistical analysis tools can be used to analyze the data and generate a list of the key yield factors for the particular data set.