Concurrent Filling Of Plurality Of Trenches Having Different Trench Shape Or Dimension, E.g., Rectangular And V-shaped Trenches, Wide And Narrow Trenches, Shallow And Deep Trenches (epo) Patents (Class 257/E21.548)
  • Patent number: 10573520
    Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a plurality of mandrels from a base structure, forming a plurality of non-mandrels including a hard mask material having an etch property substantially similar to that of the plurality of mandrels, forming photo-sensitive material or a memorization layer over the plurality of mandrels and the plurality of non-mandrels, and applying an exposure scheme to the photo-sensitive material or the memorization layer to create at least one mandrel cut pattern and at least one non-mandrel cut pattern.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Yongan Xu, Lawrence A. Clevenger, Yann Mignot, Cornelius Brown Peethala
  • Patent number: 10460982
    Abstract: A method for fabricating a semiconductor device with dual trench isolations includes forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors, forming a first shallow trench located between transistors of the first array and a second shallow trench located between transistors of the second array, and forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
  • Patent number: 10424594
    Abstract: Provided are methods of forming a thin film and methods of fabricating a semiconductor device including the same. The thin film forming methods may include supplying an organic silicon source to form a silicon seed layer on a lower layer, the silicon seed layer including silicon seed particles adsorbed on the lower layer, and supplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon atoms.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dongkak Lee
  • Patent number: 10395973
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Patent number: 10361220
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien
  • Patent number: 10236258
    Abstract: An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 ?m and a vertical extension in a range 100 nm to 1 ?m. The alignment mark further includes at least one fin within the groove at a distance of at least 60 ?m to a closest one of inner corners of the groove.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Moser, Hans Weber, Michael Treu, Johannes Baumgartl, Gabor Mezoesi
  • Patent number: 10236184
    Abstract: Initial film layers prepared from tin(II) chloride spontaneously generate open cavities when the initial film layers are thermally cured to about 400° C. using a temperature ramp of 1° C./minute to 10° C./minute while exposed to air. The openings of the bowl-shaped cavities have characteristic dimensions whose lengths are in a range of 30 nm to 300 nm in the plane of the top surfaces of the cured film layers. The cured film layers comprise tin oxide and have utility in gas sensors, electrodes, photocells, and solar cells.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Amy N. Bowers, Luisa D. Bozano, Andrea Fasoli, Krystelle Lionti, Elizabeth M. Lofano, Robert D. Miller, Linda K. Sundberg
  • Patent number: 10121677
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming, on a substrate, protruding portions with first films on the surfaces thereof, respectively, forming a second film different from the first films so as to fill a depressed portion between the protruding portions and to cover the protruding portions, processing in such a manner that the top surface of the second film on the depressed portion is higher than the top surface of the second film on the protruding portions after forming the second film to cover the protruding portions, and polishing the second film on the depressed and protruding portions to expose the first films.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yukiteru Matsui, Takahiko Kawasaki, Akifumi Gawase, Kenji Iwade
  • Patent number: 9899396
    Abstract: A method for fabricating a semiconductor device includes: forming a first trench and a wider second trench in a substrate and a material layer formed thereon, forming a flowable isolation material covering the material layer and filling in the first and second trenches, removing a portion of the flowable isolation material in the second trench so that the thickness of the remaining flowable isolation material on the sidewall of the second trench is 200 ? to 1000 ?, and forming a non-flowable isolation material on the flowable isolation material.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 20, 2018
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chih-Hsiung Lee, Chien-Ying Lee, Tzung-Ting Han
  • Patent number: 9871071
    Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: January 16, 2018
    Assignee: Sony Corporation
    Inventor: Takayuki Enomoto
  • Patent number: 9865453
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of recess regions on an upper surface of a substrate, forming a first oxide layer in the recess regions, forming a polysilicon layer on the first oxide layer, forming a second oxide layer by oxidizing the polysilicon layer, and forming a gap-fill layer on the second oxide layer to fill the recess regions, wherein at least a portion of the polysilicon layer remains between the first oxide layer and the second oxide layer after forming the second oxide layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daehyun Moon, HyeoungWon Seo, Ilgweon Kim, Jooyoung Lee, Dongjin Jung
  • Patent number: 9865496
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 9, 2018
    Assignee: SK Hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Patent number: 9853149
    Abstract: The present disclosure relates an integrated circuit (IC) and a method for manufacturing same. A polysilicon layer is formed over a first region of a substrate and has a plurality of polysilicon structures that are packed with respect to one another to define a first packing density. A dummy layer is formed over a second region of the substrate and has a plurality of dummy structures that are packed with respect to one another to define a second packing density, where the first packing density and second packing density are substantially similar. An inter-layer dielectric layer is formed over the first region and second region of the substrate. Dishing of at least the second region of the substrate concurrent with a chemical-mechanical polish is generally inhibited by the first packing density and second packing density after forming the inter-layer dielectric layer.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsuing Chen, Fu-Jier Fan, Yi-Huan Chen, Kong-Beng Thei, Ker-Hsiao Huo, Szu-Hsien Liu
  • Patent number: 9799727
    Abstract: An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Xianfeng Zhou
  • Patent number: 9773733
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 26, 2017
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 9754795
    Abstract: A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the sil
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 5, 2017
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Qiang Hua, Yaohui Zhou
  • Patent number: 9735156
    Abstract: A semiconductor device including: a fin-type pattern protruding from a substrate and including a first side surface and a second side surface opposite each other; a first trench in contact with the first side surface; a second trench in contact with the second side surface; a first liner formed conformally on a side surface and a bottom surface of the first trench; a first field insulating film disposed on the first liner and partially filling the first trench; a second liner formed conformally on a side surface of the second trench and exposing a bottom surface of the second trench; and a second field insulating film disposed on the second liner and partially filling the second trench.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: August 15, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ji-Hoon Cha
  • Patent number: 9716159
    Abstract: After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 25, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Manabu Takei
  • Patent number: 9704906
    Abstract: The performance of a solid state image sensor which is formed by performing divided exposure that exposes the entire chip by a plurality of times of exposure and in which each of a plurality of pixels arranged in a pixel array portion has a plurality of photodiodes is improved. In the divided exposure performed when the solid state image sensor is manufactured, a dividing line that divides an exposure region is defined to be located between a first photodiode and a second photodiode aligned in a first direction in an active region in a pixel and is defined to be along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: July 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masatoshi Kimura
  • Patent number: 9634122
    Abstract: Some embodiments relate to an integrated circuit (IC) including one or more field-effect transistor devices. A field effect transistor device includes source/drain regions disposed in an active region of a semiconductor substrate and separated from one another along a first direction by a channel region. A shallow trench isolation (STI) region, which has an upper STI surface, laterally surrounds the active region. The STI region includes trench regions, which have lower trench surfaces below the upper STI surface and which extend from opposite sides of the channel region in a second direction which intersects the first direction. A metal gate electrode extends in the second direction and has lower portions which are disposed in the trench regions and which are separated from one another by the channel region. The metal gate electrode has an upper portion bridging over the channel region to couple the lower portions to one another.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Chia-Ming Chang
  • Patent number: 9627518
    Abstract: A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: Joo Won Park, Kwang Sik Ko
  • Patent number: 9496358
    Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 15, 2016
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Neng-Tai Shih, Heng Hao Hsu, Yu Jing Chang, Hsu Chiang
  • Patent number: 9472572
    Abstract: Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Hui Zang
  • Patent number: 9368396
    Abstract: A gap fill treatment for via process is provided. A substrate with a plurality of openings has formed therein is provided. The substrate includes a dense pattern region and an isolated pattern region. A positive resist layer is formed to fill in the openings on the substrate, wherein the thickness of the positive resist layer on the surface of the isolated pattern region is greater than that on the surface of the dense pattern region. The positive resist layer on the surface of the substrate is exposed only. The exposed positive resist layer is developed to form a gap-filling material layer, wherein the gap-filling material layer has the same thickness in the dense pattern region and in the isolated pattern region. A reagent is coated on the surface to form a reaction layer. The reaction layer is removed so that a cap layer remained on the gap-filling material layer.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: June 14, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Hsiao-Chiang Lin, Kuan-Heng Lin
  • Patent number: 9318491
    Abstract: A semiconductor device includes a substrate, an insulating layer disposed on the substrate and having a trench exposing a surface portion of the substrate, and a channel-forming structure comprising crystalline semiconductor material. The channel-forming structure has a lower portion located in the trench and fins extending upright on the lower portion, where the fins are spaced from each other and are each narrower than an opening of the trench, and the lower portion of the channel forming structure has a higher crystal defect density than the fins of the channel forming structure.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Taeyong Kwon, Sangsu Kim, Jae-Hwan Lee
  • Patent number: 9034698
    Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Ozu, Shota Yoshimura, Hiroto Ohtake, Kosuke Kariu, Takashi Tsukamoto
  • Patent number: 9034725
    Abstract: A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-Whan Choi, Jung-Bong Yun, Chang-Won Choi
  • Patent number: 9029237
    Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Mahito Sawada, Tatsunori Kaneoka, Katsuyuki Horita
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 8999843
    Abstract: A semiconductor device and method of fabricating the device are provided, the method including providing an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; forming connection holes to the active region in the insulating layer to expose at least part of the active region, wherein the connection holes include a first portion of a first width and a second portion of a second width, the first portion of the connection holes being adjacent to the active region, and the first width being less than the second width; filling the connection holes with a metal material to form the contacts to the active region. As such, contacts formed for the active region also include a first portion of a first width and a second portion of a second width.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Steven Zhang, Liya Fu
  • Patent number: 8951885
    Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: David Barge, Pierre Morin
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8921183
    Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 30, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Jen-Jui Huang, Hung-Ming Tsai
  • Patent number: 8912069
    Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazuhiro Mizutani
  • Patent number: 8859396
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Patent number: 8853757
    Abstract: Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventor: Kevin Lee
  • Patent number: 8846490
    Abstract: A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Chen-Yu Chen
  • Patent number: 8815700
    Abstract: In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Peter J. Hopper, William French, Kyuwoon Hwang
  • Patent number: 8803207
    Abstract: In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: August 12, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Nathan Lawrence Kraft, Rodney Ridley, Gary M. Dolny, Joseph A. Yedinak, Christopher Boguslaw Kocon, Ashok Challa
  • Patent number: 8796086
    Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Neal L. Davis, Richard T. Housley, Ranjan Khurana
  • Patent number: 8785326
    Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Ming Zhang, Lifang Xu
  • Patent number: 8772126
    Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Anton Mauder
  • Patent number: 8765608
    Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8765555
    Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Damon E. Van Gerpen
  • Patent number: 8742536
    Abstract: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realization of MEMS structures of SOI wafers. A reliable dielectric insulation of adjacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches. The end portions of the trench fill that are freed from the surrounding silicon by etching are free of conductive not completely removed silicon strips in the recess including the active sensor structure. This is accomplished by slanted wall of isolation trenches. Additionally, the trench fill should be removable at the transition area in an efficient manner. The technological realization does not require specific additional process steps.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: June 3, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Karlheinz Freywald, Gisbert Hoelzer
  • Patent number: 8716138
    Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 6, 2014
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8710479
    Abstract: According to example embodiments, there is provided a semiconductor device including a substrate and an isolation layer structure. The substrate includes an active region having an upper active pattern and a lower active pattern on the upper active pattern. The active region has a first aspect ratio larger than about 13:1 and a second aspect ratio smaller than about 13:1. The first aspect ratio is defined as a ratio of a sum of heights of the upper active pattern and the lower active pattern with respect to a width of the upper active pattern. The second aspect ratio is defined as a ratio of the sum of the heights of the upper active pattern and the lower active pattern with respect to a width of the lower active pattern. The isolation layer structure is adjacent to the active region.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Kim, Yong-Kwan Kim
  • Patent number: 8703604
    Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
  • Patent number: 8703577
    Abstract: A method for fabricating a deep trench isolation structure, wherein the method comprising steps as follows: A first hard mask layer, a second hard mask layer and a third hard mask layer are firstly formed in sequence on a substrate. The third hard mask layer is then patterned using the second hard mask layer as an etching stop layer. Subsequently, a trench etching process is performed using the patterned third hard mask layer as a mask to form a deep trench in the substrate.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: April 22, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Meng-Kai Zhu
  • Patent number: 8691661
    Abstract: An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: April 8, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra