Abstract: A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and in the mask film to a depth to reach the semiconductor substrate, filling the plurality of trenches with the silicon oxide film, removing the mask film to expose the first silicon film existing between the silicon oxide films, selectively growing a second silicon film on the first silicon film, planarizing the second silicon film using an alkaline slurry exhibiting a pH of 13 or less and containing abrasive grains and a cationic surfactant, thereby obtaining a floating gate electrode film comprising the first and second silicon films, forming an interelectrode insulating film on the entire surface, and forming a control gate electrode film on the interelectrode insulating film.

Abstract: Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.

Abstract: In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.

Abstract: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: Embodiments relate to a method of manufacturing a semiconductor device.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.

Abstract: Disclosed is a method for manufacturing a semiconductor device having recess channels and asymmetrical junctions. The method includes forming an impurity region for adjusting the threshold voltage by implanting ions into a bit line junction of a semiconductor substrate, which includes storage nodes junction, the bit line junction, and channel regions between the source and bit line junctions, and portions of the channel regions of the semiconductor substrate adjacent to the bit line junction; forming recess channel trenches by etching the channel regions of the semiconductor substrate to a designated depth; forming a gate stack on the semiconductor substrate provided with the recess channel trenches; and forming the storage nodes junction and the bit line junction on the semiconductor substrate provided with the gate stack via ion implantation.

Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.

Abstract: A photon collector has a reflecting metal layer to increase photon collection efficiency in a solid state imaging sensor. The reflecting metal layer reflects incident light internally to a photosensor. A plurality of photon collectors is formed in a wafer substrate over an array of photosensors. The photon collector is formed in an opening in an insulating layer provided over each photosensor.

Abstract: A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and a fifth semiconductor layer of the first conduction type are stacked on the surfaces of the second and third semiconductor layers. The semiconductor device further comprises a control electrode formed in a trench with an insulator interposed therebetween. The trench passes through the fourth and fifth semiconductor layers and reaches the second semiconductor layer. A sixth semiconductor layer of the first conduction type is diffused from the bottom of the trench. A second main electrode is connected to the fourth and fifth semiconductor layers.

Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches are formed in the termination region. The trenches of the second plurality of trenches are filled with the dielectric material.

Abstract: An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.

Abstract: A manufacturing method for a semiconductor device includes generating on a substrate liquid-phase silanol having fluidity by causing a source gas made of a material containing silicon to react with a source gas made of a material containing oxygen, introducing the silanol into a first recess having an aspect ratio of a predetermined value wholly, and introducing the silanol into a space from a bottom to an intermediate portion in a second recess having an aspect ratio lower than the predetermined value, the first and second recesses are provided in the substrate, burying a silicon oxide film in the first recess and providing the silicon oxide film in the second recess by converting the silanol into the silicon oxide film by dehydrating condensation, and providing a dielectric film having film density higher than that of the silicon oxide film on the silicon oxide film.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.

Abstract: According to a fabrication method for an element isolation structure section, that is, STI, of the present invention, by differing the etching rate of material to be embedded in a narrow-width, that is, a small area trench section (first trench section) formed in a small isolation area, from the etching rate of a material to be embedded in a wide-width (plane shape of larger area) trench section (second trench section) formed in a large isolation area, in the etching step, dishing (recessing) that inevitably occurs in a CMP step can be reduced. Therefore, a STI having a higher level of flatness can be formed. As a result, by simple steps, deterioration of the electrical characteristics of elements that are element-isolated by STI can be reduced. That is to say, not only STI having excellent electrical characteristics, but also a semiconductor device provided with such STI, can be provided at a good level of production yield.

Abstract: A method is provided for fabricating an integrated circuit. According to the method, hollow isolating trenches are produced within a substrate, and active components are produced in and on active areas of the substrate that are between the trenches. The trenches are produced in an initial phase carried out before production of the active components and a final phase carried out after production of the active components. In the initial phase, trenches are formed in the substrate, and the trenches are filled with a fill material. In the final phase, the active components are encapsulated, accesses are created through the encapsulation material to each filled trench, the fill material is removed through each access, and the opening of each trench is plugged through the corresponding access. Also provided is an integrated that includes hollow isolating trenches within a substrate.

Abstract: A pattern formation method includes the steps of forming a flowable film made of a material with flowability; forming at least one of a concave portion and a convex portion provided on a pressing face of a pressing member onto the flowable film by pressing the pressing member against the flowable film; forming a solidified film by solidifying the flowable film, onto which the at least one of a concave portion and a convex portion has been transferred, through annealing at a first temperature with the pressing member pressed against the flowable film; and forming a pattern made of the solidified film burnt by annealing at a second temperature higher than the first temperature.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Abstract: A method for forming an isolation structure in a nonvolatile memory device includes forming a gate insulation layer, a gate conductive layer, and a hard mask over a substrate, etching the hard mask, the gate conductive layer, the gate insulation layer, and a portion of the substrate to form a trench, forming a first insulation layer over an inner surface of the trench and filled in a portion of the trench, removing the hard mask, and forming a second insulation layer over the first insulation layer and filled in the trench.

Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within the center region, and openings within the edge region. While the substrate is within the reaction chamber, a layer of insulative material is formed across the substrate. The layer is thicker over the one of the center region and edge region than over the other of the center region and edge region. The layer is exposed to an etch which removes the insulative material faster from over the one of the center region and edge region than from over the other of the center region and edge region.

Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.

Abstract: A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.

Abstract: A method for forming features in an etch layer is provided. A first mask is formed over the etch layer wherein the first mask defines a plurality of spaces with widths. A sidewall layer is formed over the first mask. Features are etched into the etch layer through the sidewall layer, wherein the features have widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed. An additional mask is formed over the etch layer wherein the additional mask defines a plurality of spaces with widths. A sidewall layer is formed over the additional mask. Features are etched into the etch layer through the sidewall layer, wherein the widths that are smaller than the widths of the spaces defined by the first mask. The mask and sidewall layer are removed.

Abstract: A method for forming etch features in an etch layer over a substrate is provided. An etch mask stack is formed over the etch layer. A first mask is formed over the etch mask stack. A sidewall layer is formed over the first mask, which reduces the widths of the spaces defined by the first mask. A first set of features is etched into the etch mask stack through the sidewall layer. The mask and sidewall layer are removed. An additional feature step is performed, comprising forming an additional mask over the etch mask stack, forming a sidewall layer over the additional mask, etching a second set of features at least partially into the etch mask stack. A plurality of features is etched into the etch layer through the first set of features and the second set of features in the etch mask stack.

Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

Abstract: The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater than 15 mTorr. A second step is removal of a portion of the oxide with an etch. A third step is an oxide deposition under a pressure of less than or equal to 10 mTorr. Methodology of the present invention can be utilized for forming trenched isolation regions, such as, for example, shallow trench isolation regions.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.

Abstract: Disclosed are embodiments of a method for forming a seal ring on a substrate that is anchored to the substrate by a number of vias. Also disclosed are embodiments of an assembly including such an anchored seal ring. In some embodiments, a seal ring may extend around the periphery of a MEMS device and may, in combination with a lid, provide a hermitic cavity enclosing the MEMS device. Other embodiments are described and claimed.

Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

Abstract: A semiconductor device includes a plurality of circuit portions of different functions each constructed by including a MOS transistor on an SOI substrate obtained by sequentially stacking a semiconductor substrate, a buried insulating film and a semiconductor layer. The semiconductor device includes first and second portions. The first circuit portion is isolated by being surrounded with a first insulating film provided on an upper portion of the semiconductor layer and a second insulating film penetrating the semiconductor layer to reach the buried insulating film.