Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

Abstract: The present disclosure uses data analytics for consumer focused autonomous data delivery in a 5G (fifth generation cellular network technology) telecommunications network. Data usage information is received at a control system, and the data usage information includes information about data downloaded by users at a venue. The data usage information includes content information about the data downloaded, the data being downloaded using a 5G telecommunications network. The data usage information is analyzed to determine content delivery using a service orchestration layer of a 5G telecommunications network in concert with smart channel monitoring tools of compatible platforms. A predictive analysis is generated using the analysis of the data usage information. A data action is initiated pertaining to the content for downloading the content, based on the predictive analysis, before demand for the downloading of the content, to provide faster service to end users at the venue.

Abstract: A semiconductor structure includes a substrate having a front surface and a back surface. The semiconductor structure further includes a first isolation structure extending from the front surface into the substrate, the first isolation structure having a depth D1 from the front surface. The semiconductor structure further includes a second isolation structure extending from the front surface into the substrate, the second isolation structure having a depth D2 from the front surface. The semiconductor structure further includes a first etching stop feature in the substrate and contacting the first isolation structure. The semiconductor structure further includes a second etching stop feature in the substrate and contacting the second isolation structure.

Abstract: A method for manufacturing a semiconductor structure including isolations includes receiving a substrate including a first region and a second region; forming a patterned hard mask, the patterned hard mask including a first opening exposing a portion of the first region and a second opening exposing a portion of the second region; removing portions of the substrate to form a first trench in the first region and to form a second trench in the second region; performing an ion implantation to a portion of the patterned hard mask in the first region and a portion of the substrate exposed from the first trench; enlarging the first opening to form a third opening over the first trench and enlarging the second opening to form a fourth opening over the second trench; and forming a first isolation by filling the first trench and a second isolation by filling the second trench.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a magnetic tunnel junction (MTJ) element includes a first magnetic layer, a second magnetic layer and a non-magnetic layer between the first and second magnetic layers, a contact layer formed underneath the MTJ element, the contact layer being formed of a first material, and a first layer formed around the contact layer, wherein the first layer in contact with a side surface of the contact layer, has a first width extending parallel to a stacking direction of the MTJ element, and a second width extending perpendicularly to the direction of extension of the first width, the second width being less than the first width.

Abstract: A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces includes increasing a surface area of at least one of the first and second surfaces. The method further includes oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time.

Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

Abstract: A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentration of the nitrogen-containing dopants in the upper sidewall is higher than that in the bottom sidewall of the trench, forming a spin-on dielectric layer filling the trench and covering the surface of the semiconductor substrate, performing a thermal oxidation process to form a silicon oxide layer covering the inner sidewall. Since the nitrogen-containing dopants can inhibit the oxidation rate and the concentration of the nitrogen-containing dopants in the upper inner sidewall is higher than that in the bottom inner sidewall of the trench, the thickness of the silicon oxide layer formed by the thermal oxidation process is larger at the bottom portion than at the upper portion of the trench.

Abstract: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.

Abstract: The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

Abstract: Embodiments relate to the lowered reliability of a device due to deterioration caused by the concentration of an electric field in the top corner of an STI. To solve the reliability problem, the STI top corners have a local oxidation of silicon, the top corners of the STI are rounded, and the STI steps are increased in a semiconductor device fabricated according to embodiments. Embodiments relate to an STI in high and low voltage regions of a semiconductor device which can be fabricated by providing a semiconductor substrate having a shallow trench isolation structure, a high voltage region and a low voltage region. A capping layer is formed over the entire surface of the top of the high voltage region and the low voltage region, including the shallow trench isolation structure. A photoresist pattern is formed over the top of the capping layer to expose the high voltage region, including a portion of the shallow trench isolation structure formed within the high voltage region.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.

Abstract: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Abstract: The present invention provides for an improvement of the interlayer adhesion property of the low-K layers in a dual damascene process. The method includes a shallow ion implantation process to bombard a bottom low-k layer for forming a densified layer on the bottom low-k layer. The densified layer can be a used as a substitute in the oxidation of the prior art to avoid the peeling phenomenon between the organic low-k layers.