Soi Together With Lateral Isolation, E.g., Using Local Oxidation Of Silicon, Or Dielectric Or Polycrystalline Material Refilled Trench Or Air Gap Isolation Regions, E.g., Completely Isolated Semiconductor Islands (epo) Patents (Class 257/E21.564)
  • Patent number: 10615072
    Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 7, 2020
    Assignee: Newport Fab, LLC
    Inventors: Arjun Kar-Roy, David J. Howard
  • Patent number: 10615071
    Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 7, 2020
    Assignee: Newport Fab, LLC
    Inventors: Arjun Kar-Roy, David J. Howard
  • Patent number: 10573639
    Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Gao, Shaoqiang Zhang, Chien-Hsin Lee
  • Patent number: 10529812
    Abstract: An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • Patent number: 10396300
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the gate dielectric. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. The openings expose portions of the gate dielectric and end portions of the channel material under the patterned resist layer. Metal contacts are formed at least within the openings. The metal contacts include a portion that contacts the end portions of the channel material and the portions of the gate dielectric exposed within the openings.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 10243060
    Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having uniform low-k inner spacers. A nanosheet stack is formed opposite a major surface of a substrate. The nanosheet stack includes multiple nanosheets. Cavities are formed between adjacent ones of the multiple nanosheets. The cavities are filled with an oxide material and portions of the oxide material are nitridized to form inner spacers positioned between the adjacent ones of the multiple nanosheets.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin H. Chao, ChoongHyun Lee, Chun W. Yeung, Jingyun Zhang
  • Patent number: 10115826
    Abstract: The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10107857
    Abstract: An optical coupler device includes, on a substrate, a first light-receiving element coupled to a first light-emitting element and a second light-receiving element coupled to a second light-emitting element. First, second, and third terminals are disposed on the first substrate. A first transistor pair and a second transistor pair are disposed on the first substrate. The first transistor pair is configured to electrically connect and disconnect the first and second terminals in response to a first light signal received by the first light-receiving element. The second transistor pair is configured to electrically connect and disconnect the second and third terminals in response to a second light signal received by the second light-receiving element.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoya Takai
  • Patent number: 10083972
    Abstract: The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the SRAM device and forming a fourth opening in the dielectric layer exposing a gate of the logic device, forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening, recessing a portion of the first sidewall spacer without recessing the second sidewall spacer, forming a strapped contact in the first and third openings, the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, the electrical connection is directly above a remaining portion of the first sidewall spacer.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9957159
    Abstract: The present invention generally relates to an ovenized platform and a fabrication process thereof. Specifically, the invention relates to an ovenized hybrid Si/SiO2 platform compatible with typical CMOS and MEMS fabrication processes and methods of its manufacture. Embodiments of the invention may include support arms, CMOS circuitry, temperature sensors, IMUs, and/or heaters among other elements.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: May 1, 2018
    Inventors: Weibin Zhu, Navid Yazdi
  • Patent number: 9947772
    Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 17, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 9942461
    Abstract: The inventive concepts provide an auto-focus image sensor and a digital image processing device including the same. The auto-focus image sensor includes a substrate including at least one first pixel used for detecting a phase difference and at least one second pixel used for detecting an image, a deep device isolation portion disposed in the substrate to isolate the first pixel from the second pixel, and a light shielding pattern disposed on the substrate of at least the first pixel. The amount of light incident on the first pixel is smaller than the amount of light incident on the second pixel by the light shielding pattern.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bumsuk Kim, Jungchak Ahn
  • Patent number: 9917021
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 9887156
    Abstract: A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the device layer and that partially extends through the buried insulator layer, at least one dielectric layer that is formed on the device layer and includes a first opening that communicates with the trench and a contact plug that fills the trench. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. The contact plug is externally connected with a source to provide signals to the back-side device structure through a wire formed in the at least one dielectric layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Patent number: 9842928
    Abstract: An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Chandra S. Mohapatra
  • Patent number: 9799720
    Abstract: The present invention relates generally to semiconductor structures and methods of manufacturing and, more particularly, to improving heat dissipation of devices, such as active devices like inductors, by filling portions of the semiconductor structure with thermally conductive and electrical isolating material that may serve as a heat sink to a base substrate. In an embodiment, an inductor may be formed above a cavity region in which the thermally conductive and electrical isolating material has been formed. Heat may then be dissipated from the inductor to the cavity, and eventually to the base substrate, through trenches filled with the thermally conductive and electrical isolating material.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Qizhi Liu, Zhenzhen Ye, Yan Zhang
  • Patent number: 9793348
    Abstract: A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: October 17, 2017
    Assignee: NXP B.V.
    Inventor: Jan Sonsky
  • Patent number: 9773670
    Abstract: A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: September 26, 2017
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventors: Deyuan Xiao, Richard R. Chang
  • Patent number: 9769931
    Abstract: A method for producing an electronic device including in a stack at least a first structure and a second structure, the structures being obtained from a first substrate and a second substrate. Marks are obtained from a pattern made on one of the substrates. Furthermore, the same supporting members are used during the bonding phase for the preparation of the marks and for the bonding phase for the assembly of the structures.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 19, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Franck Fournel, Chrystel Deguet
  • Patent number: 9678115
    Abstract: A contactless voltage sensing device configured to measure a voltage value of a conductor is provided. The contactless voltage sensing device includes a first impedance element having a first impedance, where the first impedance element is configured to be operatively coupled to the conductor. Further, the contactless voltage sensing device includes an antenna operatively coupled to the first impedance element, a second impedance element having a second impedance, where the second impedance element is formed in part by the antenna and a parasitic impedance element, and where the parasitic impedance element includes a parasitic impedance, and measurement and communication circuitry coupled to the first impedance element to measure the voltage value of the conductor.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: June 13, 2017
    Assignee: General Electric Company
    Inventors: Arun Kumar Raghunathan, Amol Rajaram Kolwalkar, Sameer Dinkar Vartak, Abhijeet Arvind Kulkarni, Charles Brendan O'Sullivan
  • Patent number: 9559134
    Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Jung-I Lin, Ta-Chun Lin, Tien-Lu Lin, Chen-Jong Wang
  • Patent number: 9536784
    Abstract: A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mukta G. Farooq, Andrew J. Martin, Jennifer A. Oakley
  • Patent number: 9406550
    Abstract: A method for forming an insulation structure in a semiconductor body includes forming a trench extending from a first surface into a semiconductor body, the trench having a first width in a horizontal direction of the semiconductor body, and forming a void spaced apart from the first surface in a vertical direction of the semiconductor body, the void having a second width in a horizontal direction that is greater than the first width, wherein the trench and the void are arranged adjacent to each other in a vertical direction.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Marko Lemke, Rolf Weis, Ralf Rudolf
  • Patent number: 9035462
    Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Qinghuang Lin
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Patent number: 8941211
    Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hong Chen, Chih-Ping Chao, Chen-Yao Tang, Yu Hung Chen
  • Patent number: 8928119
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 6, 2015
    Inventor: Glenn J. Leedy
  • Patent number: 8916950
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • Patent number: 8877606
    Abstract: A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, David R. Greenberg, Amlan Majumdar, Leathen Shi, Jeng-Bang Yau
  • Patent number: 8872305
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Patent number: 8859347
    Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: October 14, 2014
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Michael A. Stuber, Stuart B. Molin, Paul A. Nygaard
  • Patent number: 8846522
    Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: September 30, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Raymond Nicholas Vrtis, Dingjun Wu, Mark Leonard O'Neill, Mark Daniel Bitner, Jean Louise Vincent, Eugene Joseph Karwacki, Jr., Aaron Scott Lukas
  • Patent number: 8835330
    Abstract: A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Chen, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8823104
    Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Tze-Liang Lee, Pang-Yen Tsai
  • Patent number: 8802534
    Abstract: A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshihiro Komatsu, Tomoaki Moriwaka, Kojiro Takahashi
  • Patent number: 8736019
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 27, 2014
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 8722499
    Abstract: The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: May 13, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Maud Vinet, Laurent Grenouillet, Yannick Le Tiec, Nicolas Posseme
  • Patent number: 8716829
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 6, 2014
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 8674471
    Abstract: A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 18, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tomohide Terashima
  • Patent number: 8674472
    Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
  • Patent number: 8664078
    Abstract: An object is to provide a semiconductor device in which, through a simpler process, junction capacitance and power consumption can be reduced more than a conventional semiconductor device, and a manufacturing method thereof. An insulating film including an opening is formed over a base substrate and a part of a bond substrate is transferred to the base substrate, with the insulating film interposed therebetween, whereby a semiconductor film including a cavity between the semiconductor film and the base substrate is formed over the base substrate. Then, a semiconductor device including a semiconductor element such as a transistor is manufactured using the semiconductor film. The transistor includes a cavity between the base substrate and the semiconductor film used as an active layer. One cavity may be provided or a plurality of cavities may be provided.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hidekazu Miyairi
  • Patent number: 8653596
    Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8642405
    Abstract: A process for producing an adhered SOI substrate without causing cracking and peeling of a single-crystal silicon thin film. The process consists of selectively forming a porous silicon layer in a single-crystal semiconductor substrate, adding hydrogen into the single-crystal semiconductor substrate to form a hydrogen-added layer, adhering the single-crystal semiconductor substrate to a supporting substrate, separating the single-crystal semiconductor substrate at the hydrogen-added layer by thermal annealing, performing thermal annealing again to stabilize the adhering interface, and selectively removing the porous silicon layer to give single-crystal silicon layer divided into islands.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Fukunaga
  • Patent number: 8643109
    Abstract: A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8629501
    Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman
  • Patent number: 8623758
    Abstract: A method includes forming an adhesion barrier layer over a dielectric layer formed on a substrate. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. A metal layer is formed over the stress-reducing barrier layer. The metal layer, adhesion barrier layer, and stress-reducing barrier layer define an interconnect metal stack. Recesses are defined in the interconnect metal stack to expose the dielectric layer. The recesses are filled with a dielectric material, wherein a portion of the interconnect metal stack disposed between adjacent recessed filled with dielectric material defines an interconnect structure.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: January 7, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Xunyuan Zhang, Paul R. Besser
  • Patent number: 8609508
    Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove
  • Patent number: 8575699
    Abstract: SOI structures with silicon layers less than 20 nm thick are used to form ETSOI semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and lowers the drain induced bias and sub-threshold swings. The structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, during STI and contact formation.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Zhibin Ren, Xinhui Wang
  • Patent number: 8574972
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Patent number: 8551860
    Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukchul Bang, Kwangjin Moon, Byung Lyul Park, Dosun Lee, Deok-Young Jung, Gilheyun Choi