Soi Together With Lateral Isolation, E.g., Using Local Oxidation Of Silicon, Or Dielectric Or Polycrystalline Material Refilled Trench Or Air Gap Isolation Regions, E.g., Completely Isolated Semiconductor Islands (epo) Patents (Class 257/E21.564)
  • Patent number: 6800917
    Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: October 5, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky