Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.

Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

Abstract: A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space. A second air gap is on a sidewall of the second metal line and in the space. A dielectric material is disposed in the space and between the first and the second air gaps. A third air gap is underlying the lower portion of the dielectric material, wherein the first air gap, the second air gap, and the third air gap are interconnected to form a continuous air gap.

Abstract: A method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material is provided. Specifically, a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating is provided.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer.

Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.

Abstract: A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.

Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.

Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. A blocking layer can be introduced to inhibit the formation of materials in the air gaps during subsequent process steps. The blocking layer may result in selective air gap formation or varying dimension of air gaps at cell areas relative to select gate areas in the memory. The blocking layer may result in a smaller vertical dimension for air gaps formed in the isolation regions at select gate areas relative to cell areas. The blocking layer may inhibit formation of air gaps at the select gate areas in other examples. Selective etching, implanting and different isolation materials may be used to selectively define air gaps.

Abstract: A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.

Abstract: A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.

Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.

Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

Abstract: In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.

Abstract: An apparatus includes a crystalline substrate. A cleaving guide on the substrate is positioned over a cleave plane of the crystalline substrate and positioned in a known location with respect to a feature of an electronic device on the substrate. Cleaving of the substrate along the cleave plane changes a physical characteristic of the cleaving guide and measurement of the physical characteristic provides a parameter representative of the relative position of the cleave plane and the cleaving guide.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer.

Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.

Abstract: Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections.

Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.

Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removale of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.

Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.

Abstract: An integrated circuit structure includes a triple-axis accelerometer, which further includes a proof-mass formed of a semiconductor material; a first spring formed of the semiconductor material and connected to the proof-mass, wherein the first spring is configured to allow the proof-mass to move in a first direction in a plane; and a second spring formed of the semiconductor material and connected to the proof-mass. The second spring is configured to allow the proof-mass to move in a second direction in the plane and perpendicular to the first direction. The triple-axis accelerometer further includes a conductive capacitor plate including a portion directly over, and spaced apart from, the proof-mass, wherein the conductive capacitor plate and the proof-mass form a capacitor; an anchor electrode contacting a semiconductor region; and a transition region connecting the anchor electrode and the conductive capacitor plate, wherein the transition region is slanted.

Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.

Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Abstract: A semiconductor device having a spacer with an air gap is manufactured by forming a first conductive pattern over a semiconductor substrate; forming a spacer on sidewalls of the first conductive pattern; forming a sacrifice layer on sidewall of the spacer, the sacrifice layer having a different etching selectivity with the spacer; forming a second conductive pattern to fill a space between the first conductive pattern and the first conductive pattern; and forming an air gap between the first and second conductive patterns by selectively removing the sacrifice layer.

Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

Abstract: A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

Abstract: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor.

Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

Abstract: A chemical mechanical polishing (CMP) composition, comprising (A) at least one type of inorganic particles which are dispersed in the liquid medium (C), (B) at least one type of polymer particles which are dispersed in the liquid medium (C), (C) a liquid medium, wherein the zeta-potential of the inorganic particles (A) in the liquid medium (C) and the zeta-potential of the polymer particles in the liquid medium (C) are of same signs.

Abstract: An air gap fabricating method is provided. A patterned sacrificial layer is formed over a substrate, and the material of the patterned sacrificial layer includes a germanium-antimony-tellurium alloy. A dielectric layer is formed on the patterned sacrificial layer. A reactant is provided to react with the patterned sacrificial layer and the patterned sacrificial layer is removed to form a structure with an air gap disposed at the original position of the patterned sacrificial layer.

Abstract: A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

Abstract: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate, trenches are dug and delimit walls; a closing layer is epitaxially grown, that closes the trenches at the top and forms a suspended membrane; a heat treatment is performed so as to cause migration of the silicon of the walls and to form a closed cavity underneath the suspended membrane; and structures are formed for transducing the deflection of the suspended membrane into electrical signals.

Abstract: A method for producing a device with at least one suspended membrane, including the following steps: Producing a trench through a first sacrificial layer and a second layer deposited on the first sacrificial layer, the trench completely surrounding at least a portion of the first sacrificial layer and at least a portion of the second layer, filling all or a portion of the trench with at least one material capable of resisting at least one etching agent, and etching the portion of the first sacrificial layer with the etching agent through at least one opening made in the second layer, the portion of the second layer forming at least one portion of the suspended membrane.

Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.

Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: A method of forming air gaps between adjacent raised features on a substrate includes forming a carbon-containing material in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming a silicon-containing film over the carbon-containing material using a flowable deposition process, where the silicon-containing film fills an upper region between the adjacent raised features and extends over the adjacent raised features. The method also includes curing the carbon-containing material and the silicon-containing material at an elevated temperature for a period of time to form the air gaps between the adjacent raised features.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.