Memory Structures (epo) Patents (Class 257/E21.613)
  • Patent number: 10553549
    Abstract: A semiconductor device includes a transistor device implemented over an oxide layer, an interface layer applied below at least a portion of the oxide layer, the interface layer having a trench formed therein, and a substrate layer covering at least a portion of the interface layer and the trench to form a cavity.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: February 4, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: David T. Petzold, David Scott Whitefield
  • Patent number: 10541627
    Abstract: A microelectromechanical system (MEMS) device includes a substrate and a movable element at least partially suspended above the substrate and having at least one degree of freedom. The MEMS device further includes a protrusion extending from the substrate and configured to contact the movable element when the movable element moves in the at least one degree of freedom, wherein the protrusion comprises a surface having a water contact angle of higher than about 15° measured in air.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Heng Tsai, Chia-Hua Chu, Kuei-Sung Chang
  • Patent number: 9013011
    Abstract: A staggered die MEMS package includes a substrate having a converter cavity formed therein. A converter electronic component is mounted within the converter cavity. Further, a MEMS electronic component is mounted to both the substrate and the converter electronic component in a staggered die arrangement. By staggering the MEMS electronic component directly on the converter electronic component instead of locating the MEMS electronic component in a side by side arrangement with the converter electronic component, the total package width of the staggered die MEMS package is minimized. Further, by locating the converter electronic component within the converter cavity and staggering the MEMS electronic component directly on the converter electronic component, the total package height, sometimes called Z-height, of the staggered die MEMS package is minimized.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 21, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Bob Shih-Wei Kuo, Brett Arnold Dunlap, Louis B. Troche, Jr., Ahmer Syed, Russell Shumway
  • Patent number: 8975114
    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8921957
    Abstract: A MEMS microphone. The MEMS microphone includes a back plate, a membrane, a support structure, a substrate, and an overtravel stop. The membrane is coupled to the back plate. The support structure includes a support structure opening and a first side of the support structure is coupled to a second side of the back plate. The substrate includes a substrate opening and a first side of the substrate is coupled to a second side of the support structure. The overtravel stop limits a movement of the membrane away from the back plate and includes at least one of an overtravel stop structure coupled to the substrate, an overtravel stop structure formed as part of a carrier chip, and an overtravel stop structure formed as part of the support structure in the support structure opening.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 30, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Yujie Zhang, Andrew J. Doller, Thomas Buck
  • Patent number: 8895400
    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Yun-Gi Kim, Young-Woong Son, Bong-Soo Kim
  • Patent number: 8815696
    Abstract: A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8809146
    Abstract: Methods for forming semiconductor memory structures including a gap between adjacent gate structures are provided. The methods may include forming an insulation layer between the adjacent gate structures. In some embodiments, the methods may include subsequently removing a portion of the insulation layer to leave the gap between the adjacent gate structures.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daewoong Kang, Sungnam Chang, JinJoo Kim, Kyongjoo Lee, Eun-Jung Lee
  • Patent number: 8803296
    Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 12, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: William Robert Morrison, Mark Christopher Fisher, Murali Hanabe, Ganapathy Subramaniam Sivakumar, Simon Joshua Jacobs
  • Patent number: 8790976
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8779533
    Abstract: In one embodiment, a method of opening a passageway to a cavity includes providing a donor portion, forming a heating element adjacent to the donor portion, forming a first sacrificial slab abutting the donor portion, wherein the donor portion and the sacrificial slab are a shrinkable pair, forming a first cavity, a portion of the first cavity bounded by the first sacrificial slab, generating heat with the heating element, forming a first reduced volume slab from the first sacrificial slab using the generated heat and the donor portion, and forming a passageway to the first cavity by forming the first reduced volume slab.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Ando Feyh, Po-Jui Chen
  • Patent number: 8772841
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 8742386
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej S. Sandhu
  • Patent number: 8633567
    Abstract: A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: January 21, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8609475
    Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-Wen Sun, Tony Chiang, Chi-I Lang, Jinhong Tong
  • Patent number: 8569130
    Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 8558220
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (CNT) material above the first conductor; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 15, 2013
    Assignee: SanDisk 3D LLC
    Inventors: April Schricker, Mark Clark, Brad Herner
  • Patent number: 8551838
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 8541829
    Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kikuko Sugimae, Masayuki Ichige, Fumitaka Arai, Yasuhiko Matsunaga, Atsuhiro Sato
  • Publication number: 20130242649
    Abstract: Embodiments disclosed herein may relate to forming an interface between a selector transistor and a phase change material storage cell in a memory device.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Agostino Pirovano
  • Patent number: 8525142
    Abstract: A non-volatile variable resistance memory device and a method of fabricating the same are provided. The non-volatile variable resistance memory device may include a lower electrode, a buffer layer on the lower electrode, an oxide layer on the buffer layer and an upper electrode on the oxide layer. The buffer layer may be composed of an oxide and the oxide layer may have variable resistance characteristics.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: El Mostafa Bourim, Eun-Hong Lee, Choong-Rae Cho
  • Patent number: 8507353
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8476154
    Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: July 2, 2013
    Assignee: Fudan University
    Inventors: Dongping Wu, Shi-Li Zhang
  • Patent number: 8470666
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8466005
    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 18, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Dipankar Pramanik, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8450154
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Patent number: 8436410
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 7, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woong Kang, Sung-Nam Chang, Jin-Joo Kim, Kyong-Joo Lee, Eun-Jung Lee
  • Patent number: 8426268
    Abstract: The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem
  • Patent number: 8421168
    Abstract: This document discusses, among other things, a conductive frame, a silicon die coupled to the conductive frame, the silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a silicon die port extending through the silicon die to the vibratory diaphragm, with a silicon die terminal in electrical communication with the conductive frame and an insulator affixed to the conductive frame and the silicon die, with the insulator extending through interstices in the conductive frame to a conductive frame bottom of the conductive frame, and around an exterior of the silicon die to the silicon die top, with the insulator physically affixed to the silicon die and to the conductive frame, with the silicon die port exposed and with a conductive frame terminal disposed at the conductive frame bottom in electrical communication with the silicon die terminal.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: April 16, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Howard Allen, Luke England, Douglas Alan Hawks, Yong Liu, Stephen Martin
  • Patent number: 8409977
    Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each r
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunil Shim, Jaehoon Jang, Hansoo Kim, Sungmi Hwang, Wonseok Cho, Jinsoo Lim
  • Patent number: 8410562
    Abstract: A capacitive chemical sensor, along with methods of making and using the sensor are provided. The sensors described herein eliminate undesirable capacitance by etching away the substrate underneath the capacitive chemical sensor, eliminating most of the substrate capacitance and making changes in the chemical-sensitive layer capacitance easier to detect.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 2, 2013
    Assignee: Carnegie Mellon University
    Inventors: Nathan Lazarus, Gary Fedder, Sarah Bedair, Chiung Lo
  • Patent number: 8399293
    Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 19, 2013
    Assignee: Wafer-Level Packaging Portfolio LLC
    Inventors: Juergen Leib, Hidefumi Yamamoto
  • Patent number: 8395252
    Abstract: An apparatus for packaging MEMS and ICs can include a semiconductor substrate, one or more MEMS devices, an enclosure, and one or more bonding structures. The semiconductor substrate can be bonded to a portion of the surface region. The semiconductor substrate can include one or more integrated circuits. Also, the semiconductor substrate can have an upper surface region. The one or more MEMS devise can overlie an inner region of the upper surface region formed by the semiconductor substrate. The enclosure can house the one or more MEMS devices. The enclosure can overlie a first outer region of the upper surface region. Also, the enclosure can have an upper cover region. The one or more bonding structures can be provided within a second outer region of the supper surface region.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: March 12, 2013
    Assignee: mCube Inc.
    Inventor: Xiao “Charles” Yang
  • Patent number: 8361909
    Abstract: A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 ?m and less than or equal to 10 ?m, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed.
    Type: Grant
    Filed: November 26, 2011
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takaaki Nagata
  • Patent number: 8362542
    Abstract: Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woong Kang, Sung-Nam Chang, Jin-Joo Kim, Kyong-Joo Lee, Eun-Jung Lee
  • Patent number: 8362553
    Abstract: A method includes forming elongate structures on a first substrate, such that the material composition of each elongate structure varies along its length so as to define first and second physically different sections in the elongate structures. First and second physically different devices are then defined in the elongate structures. Alternatively, the first and second physically different sections may be defined in the elongate structures after they have been fabricated. The elongate structures may be encapsulated and transferred to a second substrate. The invention provides an improved method for the formation of a circuit structure that requires first and second physically different devices to be provided on a common substrate. In particular, only one transfer step is necessary.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 29, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Thomas Heinz-Helmut Altebaeumer, Stephen Day, Jonathan Heffernan
  • Patent number: 8349663
    Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: January 8, 2013
    Assignee: SanDisk 3D LLC
    Inventors: S. Brad Herner, Tanmay Kumar
  • Patent number: 8350247
    Abstract: A resistive random access memory (RRAM) having a solid solution layer and a method of manufacturing the RRAM are provided. The RRAM includes a lower electrode, a solid solution layer on the lower electrode, a resistive layer on the solid solution layer, and an upper electrode on the resistive layer. The method of manufacturing the RRAM includes forming a lower electrode, forming a solid solution layer on the lower electrode, forming a resistive layer on the solid layer and forming an upper electrode on the resistive layer, wherein the RRAM is formed of a transition metal solid solution.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-jae Lee, Young-soo Park, Ran-ju Jung, Sun-ae Seo, Dong-chul Kim, Seung-eon Ahn
  • Patent number: 8330250
    Abstract: A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.
    Type: Grant
    Filed: September 11, 2011
    Date of Patent: December 11, 2012
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8313996
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej Sandhu
  • Patent number: 8309382
    Abstract: Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: November 13, 2012
    Assignee: Advantest America, Inc.
    Inventor: Montray Leavy
  • Patent number: 8298847
    Abstract: Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the portions of the support structures underlying the movable layer include a convex sidewall. In further embodiments, a portion of the support structure extends through an aperture in the movable layer and over at least a portion of the movable layer.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 30, 2012
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Lior Kogut, Chun-Ming Wang, Chengbin Qui, Stephen Zee, Fan Zhong
  • Patent number: 8283214
    Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material such as: Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, a Ni alloy, a Pt alloy, an Ir alloy, a Ti alloy, an Al alloy, a Cu alloy, a Co alloy, an Ru alloy, and an Rh alloy.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: October 9, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-Wen Sun, Jinhong Tong, Chi-I Lang, Tony Chiang
  • Publication number: 20120228629
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 13, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Patent number: 8222106
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki Hazama
  • Patent number: 8211765
    Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: July 3, 2012
    Assignee: Northeastern University
    Inventors: Sivasubramanian Somu, Ahmed Busnaina, Nicol McGruer, Peter Ryan, George G. Adams, Xugang Xiong, Taehoon Kim
  • Patent number: 8211729
    Abstract: A method for making a microelectronic device comprising at least one electromechanical component provided with a mobile structure, the method comprising the steps of: forming in at least one fine semiconducting thin layer lying on a supporting layer, at least one bar bound to a block, said bar being intended to form a mobile structure of an electromechanical component, withdrawing a portion of the supporting layer under said bar, forming at least one passivation layer based on dielectric material around said bar, forming an encapsulation layer around the bar and covering said passivation layer, the method further comprising steps of: making metal contact and/or interconnection areas, and then suppressing the encapsulation layer around said bar.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: July 3, 2012
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Cecilia Dupre, Philippe Robert
  • Patent number: 8198715
    Abstract: A MEMS transducer includes a substrate, a membrane layer and a back-plate layer. The membrane layer is supported by the substrate. The back-plate layer is supported by the membrane layer and includes a respective sidewall portion and a respective raised portion. One or more columns, separate from the sidewall portion of the back-plate layer, connect the back-plate layer, the membrane layer and the substrate.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: June 12, 2012
    Assignee: Wolfson Microelectronics plc
    Inventors: Richard Ian Laming, Colin Robert Jenkins
  • Patent number: 8198157
    Abstract: A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Sun Sel, Jung-Dal Choi, Young-Woo Park, Jin-Taek Park
  • Patent number: 8193597
    Abstract: A device includes: a substrate having an aperture therethrough from a first side of the substrate to a second side of the substrate; a semiconductor die having an acoustic transducer, the semiconductor die being provided on the first side of the substrate such that the acoustic transducer is aligned with the aperture in the substrate; and a dual in-line package having a recess formed therein. The substrate is disposed such that the first side of the substrate faces the recess of the dual in-line package, and the semiconductor die is disposed between the first side of the substrate and the bottom surface of the recess in the dual in-line package.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: June 5, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Timothy LeClair, Bruce Beaudry