Substrate Being Semiconductor, Using Silicon Technology (epo) Patents (Class 257/E21.606)

  • Patent number: 10141316
    Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Seok Lee, Jeong Seop Shim, Mi Na Lee, Augustin Jinwoo Hong, Je Min Park, Hye Jin Seong, Seung Min Oh, Do Yeong Lee, Ji Seung Lee, Jin Seong Lee
  • Patent number: 9806088
    Abstract: A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first layers and second layers that are alternately formed. The substrate has a memory region extending in first and second directions along a surface of the substrate, a step region adjacent to the memory region in the first direction, and a peripheral region adjacent to the memory region and the step region in the second direction. The insulating layers and the wiring layers are formed on the memory region and the step region. The first and second layers are formed on the peripheral region. Each of the first layers is formed on a same level as and in contact with one of the insulating layers, and each of the second layers is formed on a same level as and in contact with one of the wiring layers.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: October 31, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Inatsuka
  • Patent number: 9034695
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 8980727
    Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Ajay Kumar
  • Patent number: 8912052
    Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact is aligned to the first transistors with less than about 40 nm alignment error, a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 8859412
    Abstract: Optoelectronic devices, such as light-emitting diodes, laser diodes, image sensors, optical detectors, etc., made by depositing (growing) one or more epitaxial semiconductor layers on a monocrystalline lamellar/layered substrate so that each layer has a wurtzite crystal structure. In some embodiments, the layers are deposited and then one or more lamellas of the starting substrate are removed from the rest of the substrate. In one subset of such embodiments, the removed lamella(s) is/are partially or entirely removed. In other embodiments, one or more lamellas of the starting substrate are removed prior to depositing the one or more wurtzite-crystal-structure-containing layer(s).
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: October 14, 2014
    Assignee: VerLASE Technologies LLC
    Inventor: Ajaykumar R. Jain
  • Patent number: 8723314
    Abstract: Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 13, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Su, Lei Fu, Edward S. Alcid
  • Publication number: 20140084412
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
  • Patent number: 8610236
    Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao, Li-Chun Tien
  • Publication number: 20130273694
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Pun Jeng
  • Patent number: 8492176
    Abstract: To provide a method of manufacturing a semiconductor device including a step of attaching a surface protective tape onto the surface of a wafer which has completed the wafer process, a step of subjecting the back surface of the wafer to back grinding, and a step of attaching a peeling assist tape onto the surface protective tape while vacuum-adsorbing the back surface of the wafer to apply a tension to the assist tape, thereby separating the surface protective tape from the wafer, wherein a vacuum suction system has a peripheral suction system for the peripheral part of the wafer and an internal suction system for the internal region of the wafer.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Haruo Amada
  • Publication number: 20130182487
    Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a first dielectric layer, a second dielectric layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the first dielectric layer to represent a data value. During read, a read bias is applied that is sufficient to cause formation of a transient bridge in the second dielectric layer, and make a conductive path through the cell if the bridge is present in the first dielectric layer. If the bridge is not present in the first dielectric layer during the read, then the conductive path is not formed. Upon removal of the read bias voltage any the conductive bridge formed in the second dielectric layer is destructed while the conductive bridge in the corresponding other first dielectric layer, if any, remains.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Inventors: FENG-MING LEE, Yu-Yu Lin
  • Publication number: 20130070508
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device including a memory array provided on a substrate, and a control circuit provided on a surface of the substrate between the substrate and the memory array, includes steps of forming, in an insulating layer covering a p-type semiconductor region and an n-type semiconductor region of the control circuit, a first contact hole communicating with the p-type semiconductor region; forming a contact plug, in contact with the p-type semiconductor region, within the first contact hole; forming, in the insulating layer, a second contact hole communicating with the n-type semiconductor region; and forming an interconnection contacting the contact plug and the n-type semiconductor region exposed within the second contact hole.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 21, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Takeshi Imamura, Hideaki Aochi
  • Publication number: 20130021060
    Abstract: Two configurable systems including: a first configurable system including a first configurable logic die connected to at least one first configurable Input-Output die, and a second configurable system including a second configurable logic die connected to at least one second configurable Input-Output die; wherein the first configurable logic die includes a multiplicity of device layers, and the second configurable logic die includes a multiplicity of device layers; wherein the first configurable logic die size is substantially larger than the second configurable logic die size, and wherein the device layers of the second configurable logic die are substantially the same as a portion of the corresponding device layers of the first configurable logic die.
    Type: Application
    Filed: January 20, 2012
    Publication date: January 24, 2013
    Inventor: Zvi Or-Bach
  • Publication number: 20120187521
    Abstract: A semiconductor device has a trench junction barrier Schottky diode that includes an integrated substrate p-n diode (TJBS-Sub-PN) as a clamping element, the trench junction barrier Schottky diode being suited, e.g., as a Zener diode having a breakdown voltage of approximately 20 V, for use in motor-vehicle generator systems. In this context, the TJBS-Sub-PN is made up of a combination of a Schottky diode, an epitaxial p-n diode and a substrate p-n diode, and the breakdown voltage of the substrate p-n diode (BV_pn) is less than the breakdown voltage of the Schottky diode (BV_schottky) and the breakdown voltage of the epitaxial p-n diode (BV_epi).
    Type: Application
    Filed: June 10, 2010
    Publication date: July 26, 2012
    Inventors: Ning Qu, Alfred Goerlach
  • Publication number: 20120154068
    Abstract: A crystal oscillator includes a cover, a crystal blank and an Integrated Circuit (IC) chip. The cover has a surface, a cavity formed in the surface, a plurality of conductive contacts and a conductive sealing ring. The conductive contacts are disposed on the surface, and the conductive sealing ring is disposed on the surface and surrounds the conductive contacts. The IC chip is connected to the conductive contacts and the conductive sealing ring, and forms a hermetic chamber with the cover and the conductive sealing ring. The crystal blank is located in the hermetic chamber, and is electrically connected to the IC chip. Furthermore, a method for manufacturing a crystal oscillator is also provided.
    Type: Application
    Filed: May 25, 2011
    Publication date: June 21, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Wen Hsu, Lung-Tai Chen, Tzung-Ching Lee, Chao-Ta Huang
  • Patent number: 8163616
    Abstract: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Daelok Bae, Jongwook Lee, Seungwoo Choi, Yong-Hoon Son, Jong-Hyuk Kang, Jung Ho Kim
  • Publication number: 20120032293
    Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Huei CHEN, Jung-Hsuan CHEN, Shao-Yu CHOU, Hung-Jen LIAO, Li-Chun TIEN
  • Publication number: 20120009695
    Abstract: The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Haruo Amada, Kenji Shimazawa
  • Publication number: 20110312157
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 22, 2011
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 8053829
    Abstract: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Daelok Bae, Jongwook Lee, Seungwoo Choi, Yong-Hoon Son, Jong-Hyuk Kang, Jung Ho Kim
  • Patent number: 8039313
    Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 18, 2011
    Assignee: Infineon Technologies AG
    Inventors: Friedrich Kroener, Francisco Javier Santos Rodriguez, Carsten von Koblinski
  • Publication number: 20110221036
    Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
    Type: Application
    Filed: May 25, 2011
    Publication date: September 15, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hisao Kawasaki
  • Patent number: 8017453
    Abstract: A method and an apparatus for manufacturing a memory cell having a nonvolatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: September 13, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Steven T. Harshfield
  • Patent number: 8003546
    Abstract: In a method of growing silicon (Si) using a reactor, a supercritical fluid including a silicon Si source and hydrogen flows in the reactor, and the Si source reacts with hydrogen. A base substrate of a solar cell may be formed with Si made using the method of growing silicon (Si). The supercritical fluid may be a fluid in which Si is not oxidized and may be, for example, a CO2 supercritical fluid with a pressure of about 60 to about 200 atm. The Si source may be TriChloroSilane (TCS) (SiCl3H) or SiH4.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Chang-soo Lee, Dong-joon Ma
  • Patent number: 7906363
    Abstract: A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 15, 2011
    Assignee: ZyCube Co., Ltd.
    Inventor: Mitsumasa Koyanagi
  • Publication number: 20110014771
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings.
    Type: Application
    Filed: January 25, 2010
    Publication date: January 20, 2011
    Inventors: Vance Dunton, Raghuveer S. Makala, Michael Chan
  • Publication number: 20100248431
    Abstract: A method for manufacturing a nonvolatile storage device including: a plurality of first electrodes aligning in a first direction; a plurality of second electrodes aligning in a second direction nonparallel to the first direction and provided above the first electrodes; and a first storage unit provided between the first electrode and the second electrode and including a first storage layer, a resistance of the first storage layer changing by at least one of an applied electric field and an applied current, the method includes: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a major surface of a substrate; processing the first electrode film and the first storage unit film into a strip shape aligning in the first direction; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the
    Type: Application
    Filed: March 18, 2010
    Publication date: September 30, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito NISHITANI, Eiji Ito, Machiko Tsukiji, Hiroyuki Fukumizu, Naoya Hayamizu, Katsuhiro Sato
  • Publication number: 20100243980
    Abstract: A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction nonparallel to the first direction; and a memory layer placed between the first interconnection and the second interconnection and reversibly transitioning between a first state and a second state by a current supplied via the first interconnection and the second interconnection. A cross section parallel to the first and the second direction of the memory layer decreases toward the second interconnection.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki FUKUMIZU
  • Publication number: 20100227439
    Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 9, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Heon Yong CHANG
  • Patent number: 7759201
    Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: July 20, 2010
    Assignee: SanDisk 3D LLC
    Inventors: Christopher J. Petti, Steven J. Radigan
  • Patent number: 7727812
    Abstract: Provided is a singulation method of a semiconductor device that can perform a sawing process while protecting a pad. In the singulation method for forming a semiconductor device including a scribe lane region and a chip region, pads are formed in the chip region. Photoresist patterns exposing the scribe lane region and covering the pads are formed, and a substrate in the scribe lane region is cut and a washing solution is sprayed on the scribe lane region. According to the method, wafers can be stably separated from each other while pads of a semiconductor device are protected, so that stabilization in the fabrication process can be realized and pad corrosion caused by DI water is prevented during a sawing process. Accordingly, a defective device is minimized and reliability of a device can improve.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 1, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Meng An Jung
  • Patent number: 7723141
    Abstract: To produce a structure of a micro-electro-mechanical system (MEMS) in a hermetic cavity (38) of a microelectronic device (50), a prepared cover (30) and substrate (10) are bonded by means of silicon direct bonding (SDB). To optimise the preparation of surfaces by means of wet cleaning without impairing the properties of the MEMS (22), i.e. without causing adhesions, the MEMS structure (22) is not released during bonding, but attached to the base (12) by means of a sacrificial intermediate layer (16). Said layer is removed once bonding has been carried out by injecting HF vapour via a vent (40) opening into the cavity (38).
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 25, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Philippe Robert
  • Publication number: 20100090306
    Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 15, 2010
    Inventors: Ali Salih, Mingjiao Liu, Thomas Keena
  • Publication number: 20100059795
    Abstract: In at least one embodiment of the invention, an apparatus includes an integrated circuit comprising a power stage portion of a power converter circuit. The power stage portion includes a first switch circuit portion formed by a first plurality of lateral devices in a first substrate. The power stage portion includes a second switch circuit portion formed by a second plurality of lateral devices in the first substrate. The integrated circuit includes a multi-layer current routing structure configured to transport a first current between the first plurality of lateral devices and an array of conductor structures on the surface of the integrated circuit using a first substantially vertical conduction path when the first switch circuit portion is enabled.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 11, 2010
    Inventor: Firas Azrai
  • Publication number: 20100006852
    Abstract: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; and a gate electrode disposed on the insulating layer over the channel region, wherein the semiconductor layer includes tapered edge portions with a taper angle defined between the tapered edge portions and a surface of the substrate is less than about 30 degrees.
    Type: Application
    Filed: December 11, 2008
    Publication date: January 14, 2010
    Inventors: Jae-Bum Park, Hyoung-Suk Jin
  • Publication number: 20090321789
    Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Chun-Ming Wang, Yung-Tin Chen, Roy E. Scheuerlein
  • Publication number: 20090290412
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Inventor: Chandra Mouli
  • Publication number: 20090243115
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other.
    Type: Application
    Filed: November 21, 2008
    Publication date: October 1, 2009
    Inventors: Myoung-jae Lee, Young-soo Park, Chang-bum Lee, Seung-eon Ahn, Ki-hwan Kim, Bo-soo Kang
  • Publication number: 20090218644
    Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of conductive lines is provided. The conductive lines are configured to guide electric currents or voltages. The conductive lines are at least partially surrounded by material which increases the electric field confinement of electric fields occurring within the conductive lines, and which functions as a diffusion barrier for material included within the conductive lines.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventor: Gill Yong Lee
  • Publication number: 20090207681
    Abstract: Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In some embodiments, the device includes a local data line connected to the first terminal, at least a portion of a capacitor plate connected to the second terminal, and a global data line connected to the local data line by the capacitor plate.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Werner Juengling
  • Publication number: 20090189195
    Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Inventors: Uwe Paul Schroeder, Chu-Hsin Liang
  • Publication number: 20090155962
    Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Inventors: Christopher J. Petti, Steven J. Radigan
  • Patent number: 7514276
    Abstract: The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further relates to taking a resistance measurement to determine a quality of alignment wherein the resistance measurement indicates a direction in which the first chip and the second chip are misaligned.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: April 7, 2009
    Assignee: International Business Machines Corporation
    Inventors: Corey Elizabeth Yearous, Phil Christopher Paone, Kelly Lynn Williams, David Paul Paulsen, Gregory John Uhlmann, John Edward Sheets, II, Karl Robert Ericson
  • Publication number: 20090052220
    Abstract: An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 26, 2009
    Inventor: Bendik Kleveland
  • Publication number: 20090029501
    Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.
    Type: Application
    Filed: October 3, 2008
    Publication date: January 29, 2009
    Applicant: ANALOG DEVICES, INC.
    Inventor: Jason W. Weigold
  • Publication number: 20090014837
    Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same. A high-resistance silicon wafer is manufactured in such a manner that a large-sized silicon wafer manufactured by the Czochralski method is irradiated with neutrons, and high-resistance and low-resistance elements are simultaneously formed on the high-resistance silicon wafer. Thus, the manufacturing cost can be remarkably saved, and the reliability of products can be enhanced.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 15, 2009
    Applicant: PETARI INCORPORATION
    Inventor: Young Jin PARK
  • Publication number: 20080303115
    Abstract: A semiconductor memory device includes a semiconductor substrate having a dummy cell region adjacent to a memory cell region, a plurality of memory cell transistors, a selective gate transistor, a peripheral circuit transistor, a selective gate line, a contact plug, a dummy contact plug formed in an element forming region of the memory cell region adjacent to the selective gate line, and a spacer insulating film formed on a sidewall of the peripheral circuit transistor. The sidewall of the selective gate electrode is formed with no spacer insulating film, and the selective gate line has a sidewall facing an region of the dummy cell region in which the dummy contact plug is formed, except for the sidewall of the selective gate electrode. The sidewall of the selective gate line is formed with a spacer insulating film.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 11, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shoichi MIYAZAKI, Tadahito Fujisawa
  • Publication number: 20080258182
    Abstract: A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
    Type: Application
    Filed: October 13, 2005
    Publication date: October 23, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Prabhat Agarwal, Jan W. Slotboom, Wibo Van Noort
  • Publication number: 20080203517
    Abstract: A semiconductor component is proposed which has a semiconductor body having a first semiconductor zone of the first conduction type, at least one first rectifying junction with respect to the first semiconductor zone, at least one second rectifying junction with respect to the first semiconductor zone, wherein the three rectifying junctions each have a barrier height of different magnitude.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Applicant: Infineon Technologies AG
    Inventors: MICHAEL RUEB, Roland Rupp, Michael Treu