Three-dimensional Integrated Circuits Stacked In Different Levels (epo) Patents (Class 257/E21.614)
  • Patent number: 10410716
    Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 10, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Miao Hu, Zhiyong Li, John Paul Strachan
  • Patent number: 10410566
    Abstract: A head mounted virtual reality display system and method is provided. The invention includes a head mounted apparatus worn by a user and a display element having an array of display regions wherein said display region contains a smaller active region having an output aperture with at least one pixel of variable color and luminosity and larger non-active region adjacent to the active region. The invention further includes means for scanning the apparent position of the active region onto the user's eye in both horizontal and/or vertical directions between a plurality of sub-frames within the display region in a pre-determined fill pattern, wherein said sub-frames cover an area including the original position of the larger non-active region and active region on the display region.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: September 10, 2019
    Inventor: Andrew Kerdemelidis
  • Patent number: 10382066
    Abstract: Disclosed is a three-dimensional TPC decoding apparatus. A three-dimensional TPC decoding apparatus includes an X decoder which decodes an X axis of an m-th upper half layer based on decoding results of a Y axis and a Z axis of an m?1-th upper half layer; a Y decoder which decodes a Y axis of an m-th lower half layer based on decoding results of an X axis and a Z axis of an m?1-th lower half layer; and a Z decoder which decodes a Z axis based on a decoding result of the Y axis of an m-th upper half layer and a decoding result of the X axis of an m-th lower half layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: August 13, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Jun Heo, Byung Kyu Ahn, Sang Chul Ha
  • Patent number: 10217666
    Abstract: A stacked structure, includes: a wiring; an insulating layer; a substrate; and a protective layer, wherein the wiring, the insulating layer, and the substrate are stacked from a bottom side, and an end portion of the wiring is projected from a side face of the stacked structure, and the protective layer is provided between the insulating layer and at least a part of the wiring and is configured of a material different from a material configuring the insulating layer.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 26, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Toshihiro Miura, Tomohide Naka, Toshiaki Hasegawa
  • Patent number: 10168534
    Abstract: The invention relates to methods and systems for augmented reality. The invention more particularly provides head-mounted devices for the display and visualization of computer-generated information content by a wearer. The invention further provides related methods and uses.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: January 1, 2019
    Assignee: Essilor International
    Inventors: Benoit Callier, Coralie Barrau
  • Patent number: 10163897
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Tang Lin, Clement Hsingjen Wann, Neng-Kuo Chen
  • Patent number: 10151717
    Abstract: The invention relates to lubricant analysis, and to apparatus and methods for carrying out real-time in situ lubricant analysis. The invention extends to apparatus and methods which can measure tribological wear in machinery and, in particular, to the in situ measurement of the elemental composition of lubricant and/or debris caught in a filter within a lubricant-wetted machine.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: December 11, 2018
    Assignee: The University of Sussex
    Inventors: John Lees, David Bassford, Anna Barnett
  • Patent number: 10121964
    Abstract: Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Juan Boon Tan, Yi Jiang, Daxiang Wang, Fan Zhang, Francis Poh, Danny Pak-Chum Shum
  • Patent number: 10068919
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chin-Sheng Yang
  • Patent number: 10043798
    Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 7, 2018
    Assignee: IMEC VZW
    Inventors: Stefan Cosemans, Praveen Raghavan, Steven Demuynck, Julien Ryckaert
  • Patent number: 9987836
    Abstract: The present disclosure provides a method and device for removing an integrated circuit. The device is used to remove the integrated circuit from a display panel. The device includes a heating unit configured to contact and heat the display panel, and a retractable clamping-taking component configured to clamp and take the integrated circuit on the display panel which has been heated. According to embodiments of the present disclosure, the method and device may remove the integrated circuit from the display panel without destroying the display panel and increase efficiency of removing the integrated circuit.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: June 5, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yong Sun, Xianzhen Tang, Zhiyu Qian, Long Yan, Jun Zhang, Daocheng Zhu, Wei Wang
  • Patent number: 9939691
    Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate; a gate line formed on the first substrate; an insulating layer formed on the gate line; and a first subpixel electrode and a second subpixel electrode that are formed on the insulating layer. Each of the first subpixel electrode and the second, subpixel electrode includes a first subregion and a second subregion. At least one of the first subregion and the second subregion includes a vertical stem, a horizontal stem extending from a middle of the vertical stem, and a plurality of minute branches laterally extending in a diagonal direction from the horizontal stem. The plurality of minute branches laterally extending from the horizontal stem are alternately branched with reference to the horizontal stem.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheol Shin, Hak Sun Chang, Ka Eun Kim, Se Hyun Lee, Ki Chul Shin
  • Patent number: 9875789
    Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
  • Patent number: 9793276
    Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: October 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Shuhei Nagatsuka, Hiroki Inoue, Takanori Matsuzaki
  • Patent number: 9780093
    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 9754521
    Abstract: A display driving circuit in accordance with the inventive concepts may include a source amplifier. The source amplifier may include an output transistor configured to amplify an input signal to generate an output signal, and charge a source line of a display panel using the output signal. The source amplifier may include an output transistor switch configured to control the output transistor, and a switch control block configured to receive configuration bits including on/off time information of the output transistor switch to generate a switch control signal. The on/off time information includes information for turning on the output transistor switch in synchronization with a horizontal synchronous signal associated with the display panel, and information for turning off the output transistor switch at a time when the source line of the display panel is charged to a desired charge level.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: September 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Young Ryu, Hyunsang Park, Sungpil Choi
  • Patent number: 9672935
    Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 6, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ronald L Cline, Stewart Logie
  • Patent number: 9595215
    Abstract: A method for testing a display panel includes: applying a first level signal to a first sub-pixel and a third sub-pixel of a first pixel unit and applying a second level signal to a second sub-pixel of the first pixel unit; applying the second level signal to a first sub-pixel and a third sub-pixel of a second pixel unit and applying the first level signal to a second sub-pixel of the second pixel unit; and detecting a short circuit between adjacent sub-pixels. The first level signal has a voltage polarity opposite to a voltage polarity of the second level signal. Therefore, it is ensured that any two adjacent sub-pixels have opposite voltage polarities when the short circuit between adjacent sub-pixels of the display panel is detected. The method also provides improved testing abilities to detect an open circuit in a sub-pixel.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 14, 2017
    Assignees: SHANGHAI AVIC OPTO ELECTRONICS CO., LTD., TIANMA MICRO ELECTRONICS CO., LTD.
    Inventors: Xu Yang, Nana Tian, Xupeng Wang, Zhiyong Ren, Xiaoyuan Ding, Zhengyuan Huang
  • Patent number: 9449886
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Hsin-Ying Lin, Mei-Yun Wang, Hsiao-Chiu Hsu, Shih-Wen Liu
  • Patent number: 9425213
    Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 23, 2016
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 9024300
    Abstract: An apparatus including: a stacked structure including a first substrate having a flat surface; a flat first graphene layer adjacent the flat surface of the first substrate; a flat second graphene layer adjacent the flat first graphene layer; and a second substrate having a flat surface adjacent the flat second graphene layer. An apparatus including: a stacked structure including a substrate having a flat upper surface; a flat lower patterned layer overlying the flat upper surface of the substrate and including at least one patterned electrode; a flat lower graphene layer overlying the flat lower patterned layer; a flat upper graphene layer overlying the flat lower graphene layer; and a flat upper patterned layer overlying the flat upper graphene layer and including at least one patterned electrode.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: May 5, 2015
    Assignee: Nokia Corporation
    Inventors: Martti Kalevi Voutilainen, Pirjo Pasanen
  • Patent number: 9024423
    Abstract: A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Muto, Yuichi Machida, Nobuya Koike, Atsushi Fujiki, Masaki Tamura
  • Patent number: 9023688
    Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.
    Type: Grant
    Filed: June 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Albert Karl Henning
  • Patent number: 9024291
    Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Han Woo Cho, Hyo Seob Yoon, Yong Seok Lee
  • Patent number: 8999844
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 8987053
    Abstract: A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Suresh Upadhyayula, Hem Takiar
  • Patent number: 8975755
    Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Xintec Inc.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin
  • Patent number: 8975117
    Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Fong Lim, Abdul Rahman Mohamed, Chooi Mei Chong, Ida Fischbach, Xaver Schloegel, Juergen Schredl, Josef Hoeglauer
  • Patent number: 8969102
    Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Peter S. Schultz
  • Patent number: 8969200
    Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 3, 2015
    Assignee: The Research Foundation of State University of New York
    Inventors: Jeremiah Hebding, Megha Rao, Colin McDonough, Matthew Smalley, Douglas Duane Coolbaugh, Joseph Piccirillo, Jr., Stephen G. Bennett, Michael Liehr, Daniel Pascual
  • Patent number: 8956959
    Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after the first monocrystalline layer has been formed; transferring the second monocrystalline layer overlying the isolation layer; and then performing a second lithography step patterning portions of the first monocrystalline layer as part of forming at least one transistor in the first monocrystalline layer.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: February 17, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 8941230
    Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Kyozuka, Akihiko Tateiwa, Yuji Kunimoto, Jun Furuichi
  • Patent number: 8933516
    Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: January 13, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Ming-Che Wu, Wei-Te Wu, Yung-Tin Chen
  • Patent number: 8816494
    Abstract: Semiconductor device packages comprise a first semiconductor device comprising a heat-generating region located on at least one end thereof. A second semiconductor device is attached to the first semiconductor device. At least a portion of the heat-generating region extends laterally beyond at least one corresponding end of the second semiconductor device. A thermally insulating material at least partially covers the end of the second semiconductor device. Methods of forming a semiconductor device packages comprise attaching a second semiconductor device to a first semiconductor device. The first semiconductor device comprises a heat-generating region at an end thereof. At least a portion of the heat-generating region extends laterally beyond an end of the second semiconductor device. The end of the second semiconductor device is at least partially covered with a thermally insulating material.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: August 26, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Steven Groothuis, Jian Li, Shijian Luo
  • Patent number: 8772920
    Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: July 8, 2014
    Assignee: Oracle International Corporation
    Inventors: Hiren D. Thacker, John E. Cunningham, Ivan Shubin, Ashok V. Krishnamoorthy
  • Patent number: 8766459
    Abstract: Capacitive micromachined ultrasonic transducer (“CMUT”) devices and fabrication methods are provided. The CMUT devices can include integrated circuit devices utilizing direct connections to various CMOS electronic components. The use of integrated connections can reduce overall package size and improve functionality for use in ultrasonic imaging applications. CMUT devices can also be manufactured on multiple silicon chip layers with each layer connected utilizing through silicon vias (TSVs). External power connections can be provided if high biasing voltages are required. Forward and side looking CMUT arrays can be manufactured for use in a variety of ultrasound technologies.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: July 1, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: F. Levent Degertekin, Gokce Gurun, Jaime Zahorian, Michael Hochman
  • Patent number: 8760909
    Abstract: A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: June 24, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jyun-Siang Huang, Wen-Jer Tsai
  • Patent number: 8748971
    Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Junya Matsunami, Ryouhei Kirisawa
  • Patent number: 8748288
    Abstract: A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Zhengwen Li, Zhijiong Luo, Huilong Zhu
  • Patent number: 8742476
    Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: June 3, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist
  • Patent number: 8735902
    Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John Zahurak, Siddartha Kondoju, Haitao Liu, Nishant Sinha
  • Patent number: 8716780
    Abstract: A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: May 6, 2014
    Assignee: Rambus Inc.
    Inventors: Mark D. Kellam, Gary B. Bronner
  • Patent number: 8716876
    Abstract: Systems and methods for stacking a memory chip with respect to an integrated circuit (IC) chip are described. In the systems and methods, a plurality of like memory chips are stacked above one or more IC chip members of a family. The use of a plurality of like memory chips for the family may save costs and complications involved in designing, fabricating, and assembling memory chips of different sizes. The use of a plurality of the memory chips on a single IC chip can enable higher data transfer rates due to parallel data transmission.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Richard G. Smolen, Jon M. Long
  • Patent number: 8709938
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 29, 2014
    Assignee: Ziptronix, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Patent number: 8703597
    Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 22, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak Sekar, Zvi Or-Bach, Brian Cronquist
  • Patent number: 8697495
    Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: April 15, 2014
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
  • Patent number: 8664042
    Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 4, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Patent number: 8652877
    Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: February 18, 2014
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Patent number: 8625381
    Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Cheol Lee
  • Patent number: 8574982
    Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams