With Particular Manufacturing Method Of Gate Conductor, E.g., Particular Materials, Shapes (epo) Patents (Class 257/E21.621)
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Patent number: 8093146Abstract: A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a hard mask layer over the gate material layers; patterning the hard mask layer to from a hard mask pattern; forming a spacer layer over the hard mask pattern; etching back the spacer layer to form spacers over sidewalls of the hard mask pattern; etching the gate material layers by using the spacers and the hard mask pattern as an etching mask to form a gate structure; and performing a tilt-angle ion implantation process to the semiconductor substrate.Type: GrantFiled: March 17, 2010Date of Patent: January 10, 2012Inventor: Shiang-Bau Wang
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Patent number: 8071445Abstract: In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench.Type: GrantFiled: April 20, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventor: Kei Takehara
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Patent number: 8044433Abstract: A semiconductor device includes a substrate, a GaN-based semiconductor layer formed on the substrate, a gate electrode embedded in the GaN-based semiconductor layer, a source electrode and a drain electrode formed on both sides of the gate electrode, a first recess portion formed between the gate electrode and the source electrode, and a second recess portion formed between the gate electrode and the drain electrode. The first recess portion has a depth deeper than that of the second recess portion.Type: GrantFiled: March 30, 2006Date of Patent: October 25, 2011Assignee: Eudyna Devices Inc.Inventors: Takeshi Kawasaki, Ken Nakata, Seiji Yaegashi
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Patent number: 8039334Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.Type: GrantFiled: October 12, 2010Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
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Patent number: 8034692Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.Type: GrantFiled: October 20, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert R. Robison
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Publication number: 20110198700Abstract: A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.Type: ApplicationFiled: February 16, 2011Publication date: August 18, 2011Inventors: Won-Kyung Park, Satoru Yamada, Young Jin Choi, Kyo-Suk Chae
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Patent number: 7994008Abstract: A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.Type: GrantFiled: January 26, 2007Date of Patent: August 9, 2011Assignee: STMicroelectronics (Crolles 2) SASInventors: Romain Wacquez, Philippe Coronel, Damien Lenoble, Robin Cerutti, Thomas Skotnicki
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Publication number: 20110165753Abstract: A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed.Type: ApplicationFiled: March 17, 2011Publication date: July 7, 2011Applicant: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Publication number: 20110159678Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuang-Yuan Hsu, Da-Yuan Lee, Wei-Yang Lee, Hun-Jan Tao
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Publication number: 20110156166Abstract: The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo Bin Huang, Ssu-Yi Li, Ryan Chia-Jen Chen, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
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Patent number: 7964465Abstract: A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.Type: GrantFiled: April 17, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Andres Bryant, Edward Joseph Nowak
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Patent number: 7960761Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.Type: GrantFiled: November 9, 2009Date of Patent: June 14, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sung Woong Chung, Sang Don Lee
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Publication number: 20110136313Abstract: Provided is a method for manufacturing a MOS transistor.Type: ApplicationFiled: November 9, 2010Publication date: June 9, 2011Inventors: Jongwon Lee, Boun Yoon, Sang Yeob Han, Chae Lyoung Kim
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Patent number: 7951678Abstract: Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700 mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V.Type: GrantFiled: August 12, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7915713Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.Type: GrantFiled: July 30, 2008Date of Patent: March 29, 2011Assignee: Qimonda AGInventors: Juergen Faul, Juergen Holz
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Patent number: 7892957Abstract: A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.Type: GrantFiled: September 18, 2008Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventor: Steven Arthur Vitale
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Publication number: 20110027951Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.Type: ApplicationFiled: October 12, 2010Publication date: February 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
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Patent number: 7871910Abstract: A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is performed. A second conductive layer is formed on the crystallized first conductive layer. A first etch process to pattern the second conductive layer is performed. A second etch process to remove an oxide layer on the crystallized first conductive layer is performed. A third etch process to pattern the amorphous first conductive layer is performed.Type: GrantFiled: June 11, 2008Date of Patent: January 18, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jae Jung Lee
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Patent number: 7871913Abstract: A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.Type: GrantFiled: December 16, 2008Date of Patent: January 18, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jong Han Shin, Hyung Soon Park, Jum Yong Park, Sung Jun Kim
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Patent number: 7863677Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a plurality of active regions which are defined in a semiconductor substrate, a plurality of gate lines which are formed as zigzag lines, extend across the active regions, are symmetrically arranged, and define a plurality of first regions and a plurality of second regions therebetween, and wherein the first regions being narrower than the second regions. The semiconductor device further includes an insulation layer which defines a plurality of contact regions by filling empty spaces in the first regions between the gate lines and, extending from the first regions, and surrounding sidewalls of portions of the gate lines in the second regions, and wherein the contact regions partially exposing the active regions and a plurality of contacts which respectively fill the contact regions.Type: GrantFiled: September 17, 2008Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Chul Park, Sang-Sup Jeong
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Patent number: 7855411Abstract: The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source/drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source/drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.Type: GrantFiled: December 17, 2007Date of Patent: December 21, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Tzu-Hsuan Hsu, Hang-Ting Lue
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Patent number: 7855141Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: July 13, 2009Date of Patent: December 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
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Publication number: 20100317182Abstract: A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.Type: ApplicationFiled: August 25, 2010Publication date: December 16, 2010Inventors: Tian-Fu Chiang, Li-Wei Cheng, Che-Hua Hsu, Chih-Hao Yu, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Publication number: 20100311231Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: ApplicationFiled: June 4, 2009Publication date: December 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Publication number: 20100301427Abstract: In a replacement gate approach in sophisticated semiconductor devices, a tantalum nitride etch stop material may be efficiently removed on the basis of a wet chemical etch recipe using ammonium hydroxide. Consequently, a further work function adjusting material may be formed with superior uniformity, while the efficiency of the subsequent adjusting of the work function may also be increased. Thus, superior uniformity, i.e., less pronounced transistor variability, may be accomplished on the basis of a replacement gate approach in which the work function of the gate electrodes of P-channel transistors and N-channel transistors is adjusted after completing the basic transistor configuration.Type: ApplicationFiled: May 21, 2010Publication date: December 2, 2010Inventors: Markus Lenski, Klaus Hempel, Vivien Schroeder, Robert Binder, Joachim Metzger
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Publication number: 20100255668Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroshi NOMURA, Takashi Saiki, Tsunehisa Sakoda
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Publication number: 20100244141Abstract: During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.Type: ApplicationFiled: March 29, 2010Publication date: September 30, 2010Inventors: Sven Beyer, Markus Lenski, Richard Carter, Klaus Hempel
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Patent number: 7781849Abstract: Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer.Type: GrantFiled: December 3, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-min Baek, Seong-hwee Cheong, Gil-heyun Choi, Tae-ho Cha, Hee-sook Park, Byung-hak Lee, Jae-hwa Park
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Patent number: 7776680Abstract: Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).Type: GrantFiled: January 3, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, John M. Cotte, Hariklia Deligianni, Toshiharu Furukawa, Vamsi K. Paruchuri, William R. Tonti
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Publication number: 20100181620Abstract: A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.Type: ApplicationFiled: January 19, 2009Publication date: July 22, 2010Applicant: International Business Machines CorporationInventors: Roger A. Booth, JR., Kangguo Cheng, Chandrasekharan Kothandaraman, Chengwen Pei
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Patent number: 7745326Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: July 13, 2009Date of Patent: June 29, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
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Patent number: 7727820Abstract: This disclosure relates to misalignment-tolerant processes for fabricating multiplexing/demultiplexing architectures. One process enables fabricating a multiplexing/demultiplexing architecture at a tolerance greater than a pitch of conductive structures with which the architecture is capable of communicating. Another process can enable creation of address elements and conductive structures having substantially identical widths.Type: GrantFiled: April 30, 2004Date of Patent: June 1, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Xiaofeng Yang, Sriram Ramamoorthi, Galen H. Kawamoto
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Patent number: 7723189Abstract: A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.Type: GrantFiled: December 29, 2006Date of Patent: May 25, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong Seok Eun, Su Ho Kim, An Bae Lee, Hai Won Kim
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Publication number: 20100124818Abstract: The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.Type: ApplicationFiled: September 25, 2009Publication date: May 20, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Da-Yuan Lee, Jian-Hao Chen, Chi-Chun Chen, Matt Yeh, Hsing-Jui Lee
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Patent number: 7718545Abstract: A fabrication process, including forming one or more layers on at least a sidewall of a topographical feature of a substantially planar substrate, the sidewall being substantially orthogonal to the substrate; and planarizing respective portions of the one or more layers to form a planar surface substantially parallel to the substrate, wherein the planar surface includes respective co-planar surfaces of the one or more layers, at least one of the surfaces having a dimension determined by a thickness of the corresponding layer.Type: GrantFiled: October 30, 2006Date of Patent: May 18, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Hou Tee Ng, Alfred I-Tsung Pan
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Patent number: 7713827Abstract: Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to prevent generation of a void when a device isolation structure is formed by a Shallow Trench Isolation (STI) method, and to prevent formation of stress between the semiconductor substrate and the FOX.Type: GrantFiled: November 5, 2007Date of Patent: May 11, 2010Assignee: Hynix Semiconductor Inc.Inventor: Yeong Eui Hong
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Patent number: 7714380Abstract: A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.Type: GrantFiled: November 13, 2007Date of Patent: May 11, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Tae-Hong Lim
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Patent number: 7701034Abstract: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.Type: GrantFiled: November 17, 2005Date of Patent: April 20, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Kong-Beng Thei, Cheng-Cheng Kuo
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Patent number: 7696075Abstract: A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.Type: GrantFiled: March 25, 2008Date of Patent: April 13, 2010Assignee: Nanya Technology CorporationInventors: Chien-An Yu, Te-Yin Chen, Hai-Han Hung
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Patent number: 7692222Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.Type: GrantFiled: November 7, 2006Date of Patent: April 6, 2010Assignee: Raytheon CompanyInventors: Kamal Tabatabaie, Robert B. Hallock
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Publication number: 20100052067Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.Type: ApplicationFiled: April 16, 2009Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
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Patent number: 7651898Abstract: First gate lines are formed on a substrate. An insulation layer is formed on the substrate and the first gate lines. The insulation layer disposed between the first gate lines is selectively etched, to thereby form first openings. Landing plugs are buried into the first openings. The insulation layer disposed on the first gate lines is etched until upper portions of the first gate lines are exposed, thereby obtaining second openings. Second gate lines are formed inside the second openings.Type: GrantFiled: December 27, 2005Date of Patent: January 26, 2010Assignee: Hynix Semiconductor Inc.Inventor: Dae-Young Seo
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Publication number: 20090302374Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Inventors: Brent A. Anderson, Suk Hoon Ku, Edward J. Nowak
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Publication number: 20090286370Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Inventors: Eliyahou Harari, George Samachisa, Jack H. Yuan, Daniel C. Guterman
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Patent number: 7615449Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.Type: GrantFiled: September 29, 2006Date of Patent: November 10, 2009Assignee: Hynix Semiconductor Inc.Inventors: Sung Woong Chung, Sang Don Lee
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Publication number: 20090275179Abstract: Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).Type: ApplicationFiled: January 3, 2008Publication date: November 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, John M. Cotte, Hariklia Deligianni, Toshiharu Furukawa, Vamsi K. Paruchuri, William R. Tonti
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Patent number: 7611979Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.Type: GrantFiled: February 12, 2007Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Renee T. Mo, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri, Sufi Zafar
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Publication number: 20090250770Abstract: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.Type: ApplicationFiled: April 7, 2008Publication date: October 8, 2009Applicant: ALPHA & OMEGA SEMICONDUCTOR, LTD.Inventors: Yi Su, Anup Bhalla, Daniel Ng
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Patent number: 7589014Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: November 30, 2006Date of Patent: September 15, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
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Patent number: 7585734Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.Type: GrantFiled: March 5, 2008Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Woong Kang, Jong-hyon Ahn