Field-effect Technology (epo) Patents (Class 257/E21.615)

  • Patent number: 10170556
    Abstract: A semiconductor device manufacturing method includes preparing a semiconductor substrate of a first conductivity type, forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate, forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate, forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction, and covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Wataru Sumida, Akihiro Shimomura
  • Patent number: 8946064
    Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
  • Patent number: 8906771
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Patent number: 8890168
    Abstract: An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuang Zhao
  • Patent number: 8802522
    Abstract: Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: August 12, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Michael G. Ward, Igor V. Peidous, Sunny Chiang, Yen B. Ta, Andrew Darlak, Peter I. Porshnev, Swaminathan Srinivasan
  • Patent number: 8767404
    Abstract: Integrated circuits with decoupling capacitor circuitry are provided. The decoupling capacitor circuitry may include density-compliance structures. The density-compliance structures may be strapped to metal paths driven by power supply lines. Strapping density-compliance dummy structures in this way may increase the capacitance per unit area of the decoupling capacitor circuitry. Strapping density-compliance dummy structures in this way may shield the decoupling capacitor from nearby noisy signal sources.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Altera Corporation
    Inventor: Chin Hieang Khor
  • Patent number: 8729630
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: May 20, 2014
    Assignee: Richtek Tehnology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Patent number: 8709900
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Publication number: 20140091845
    Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Han Wui THEN, Sansaptak DASGUPTA, Gerhard SCHROM, Valluri R. RAO, Robert S. CHAU
  • Publication number: 20140073039
    Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage.
    Type: Application
    Filed: September 8, 2012
    Publication date: March 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Shih-Wei Lin, Yi-Shao Liu
  • Patent number: 8653594
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: February 18, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Publication number: 20130334599
    Abstract: A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Ji Pan, Daniel Ng, Anup Bhalla
  • Patent number: 8609493
    Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hideo Yamamoto, Kei Takehara
  • Publication number: 20130248947
    Abstract: In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Inventors: Sunglyong Kim, Jongjib Kim
  • Publication number: 20130207200
    Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hung LU, Song-Bor LEE, Ching-Kun HUANG, Ching-Chen HAO
  • Patent number: 8435850
    Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: May 7, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20130075823
    Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Hong YU, Huang LIU
  • Publication number: 20130049076
    Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Inventor: Donald R. Disney
  • Publication number: 20130052781
    Abstract: A method of forming a Non-planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI is formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Sheng-Huei Dai, Rai-Min Huang, Chen-Hua Tsai, Shih-Hung Tsai, Chien-Ting Lin
  • Patent number: 8377777
    Abstract: A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 19, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
  • Patent number: 8373208
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 12, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 8373237
    Abstract: Example embodiments provide a transistor and a method of manufacturing the same. The transistor may include a channel layer formed of an oxide semiconductor and a gate having a three-dimensional structure. A plurality of the transistors may be stacked in a perpendicular direction to a substrate. At least some of the plurality of transistors may be connected to each other.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: February 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Park, Chang-jung Kim, I-hun Song, Sang-wook Kim, Jae-chul Park
  • Publication number: 20130009254
    Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Christian Russ, Gunther Lehmann, Franz Ungar
  • Publication number: 20130001664
    Abstract: Integrated circuits with decoupling capacitor circuitry are provided. The decoupling capacitor circuitry may include density-compliance structures. The density-compliance structures may be strapped to metal paths driven by power supply lines. Strapping density-compliance dummy structures in this way may increase the capacitance per unit area of the decoupling capacitor circuitry. Strapping density-compliance dummy structures in this way may shield the decoupling capacitor from nearby noisy signal sources.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventor: Chin Hieang Khor
  • Patent number: 8338872
    Abstract: Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69?) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94?) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94?) may be external to the transistor (69, 69?), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69?-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: December 25, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishnu K. Khemka, Tahir A. Khan, Ronghua Zhu, Weixiao Huang, Bernhard H. Grote
  • Publication number: 20120280206
    Abstract: A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
    Type: Application
    Filed: July 20, 2012
    Publication date: November 8, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Publication number: 20120267684
    Abstract: A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 25, 2012
    Applicant: Sony Corporation
    Inventors: SHINICHI TAMARI, MITSUHIRO NAKAMURA, KOJI WAKIZONO, TOMOYA NISHIDA, YUJI IBUSUKI
  • Publication number: 20120270376
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.
    Type: Application
    Filed: July 6, 2012
    Publication date: October 25, 2012
    Inventors: Dongyean Oh, Woon-kyung Lee
  • Patent number: 8288798
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a buffer layer over a substrate, the buffer layer containing a first compound semiconductor that includes elements from one of: III-V families of a periodic table; and II-VI families of the periodic table. The method includes forming a channel layer over the buffer layer. The channel layer contains a second compound semiconductor that includes elements from the III-V families of the periodic table. The method includes forming a gate over the channel layer. The method includes depositing impurities on regions of the channel layer on either side of the gate. The method includes performing an annealing process to activate the impurities in the channel layer.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthias Passlack
  • Publication number: 20120249160
    Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
    Type: Application
    Filed: June 14, 2012
    Publication date: October 4, 2012
    Applicants: FREESCALE SEMICONDUCTOR, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Rajeevakumar V. Thekkemadathil, Keith Kwong Hon Wong
  • Patent number: 8274081
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Publication number: 20120225524
    Abstract: The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor.
    Type: Application
    Filed: May 10, 2012
    Publication date: September 6, 2012
    Inventors: Yung-Chang Lin, Kuei-Sheng Wu, Chang-Chien Wong
  • Publication number: 20120187483
    Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
    Type: Application
    Filed: April 20, 2011
    Publication date: July 26, 2012
    Inventors: Ching-Yao Yang, Tsung-Yi Huang, Huan-Ping Chu, Hung-Der Su
  • Patent number: 8227309
    Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: July 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8222109
    Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hideo Yamamoto, Kei Takehara
  • Patent number: 8183101
    Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Mulfinger, Andy Wei, Jan Hoentschel, Andrew Waite
  • Publication number: 20120104468
    Abstract: Fabricating high voltage transistors includes forming a buried p-type implant on a p-substrate for each transistor, the transistor having a source side and a drain side, wherein the p-type implant is positioned adjacent the source and is configured to extend under a gate region; depositing a low doping epitaxial layer on the p-substrate and the p-type implant for each high voltage transistor, the low doping epitaxial layer extending from the source to the drain; forming an N-Well in the low doping epitaxial layer for each transistor, wherein the N-Well corresponds to a low voltage transistor N-Well fabricated using a low voltage transistor fabrication process; and forming a p-top diffusion region in or on the N-Well for each transistor, wherein the p-top diffusion region is configured to compensate for a dopant concentration of the N-Well at or near a surface of the N-Well opposing the substrate.
    Type: Application
    Filed: September 19, 2011
    Publication date: May 3, 2012
    Applicant: O2MICRO, INC.
    Inventors: Yanjun Li, Sen Zhang
  • Patent number: 8148217
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Patent number: 8148798
    Abstract: The semiconductor device includes a capacitor 36 formed over a semiconductor substrate 10 and including a lower electrode 30, a dielectric film 32 and an upper electrode 34; a first insulation film 58 formed above the capacitor 36; a first interconnection 88a formed over the first insulation film 68; a second insulation film 90 formed over the first insulation film 68 and over the first interconnection 88a; an electrode pad 102 formed over the second insulation film 90: and a monolithic conductor 100 buried in the second insulation film 90 immediately below the electrode pad 102 and buried through the second insulation film 90 down to a part of at least the first insulation layer 68.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiro Yamagata
  • Publication number: 20120074896
    Abstract: A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Sik Lui, Wei Wang
  • Patent number: 8143117
    Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: March 27, 2012
    Assignee: Au Optronics Corporation
    Inventors: Ming-Wei Sun, Chen-Yueh Li, Yu-Cheng Chen, Chia-Tien Peng
  • Publication number: 20120056273
    Abstract: A semiconductor device includes: a first transistor formed on a semiconductor substrate; and a second transistor formed above the semiconductor substrate with an insulation film interposed therebetween. The first transistor includes a first body region formed on a surface of the semiconductor substrate, and a first source region and a first drain region formed so as to sandwich the first body region, the second transistor includes a semiconductor layer formed on the insulation film, a second body region formed in a part of the semiconductor layer, a second source region and a second drain region formed so as to sandwich the second body region in the semiconductor layer, agate insulation film formed on the body region of the semiconductor layer, and agate electrode formed on the gate insulation film, and the second drain region is disposed on the first body region.
    Type: Application
    Filed: August 26, 2011
    Publication date: March 8, 2012
    Applicant: SONY CORPORATION
    Inventors: Yuji Ishii, Yuji Ibusuki, Hideki Tanaka, Kentaro Kasai
  • Publication number: 20110260262
    Abstract: A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.
    Type: Application
    Filed: September 17, 2010
    Publication date: October 27, 2011
    Applicant: Institute of Microelectronics, Chinese Academy of
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
  • Patent number: 8043904
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Izumida, Sanae Ito, Takahisa Kanemura
  • Publication number: 20110256674
    Abstract: A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Katsura Miyashita
  • Patent number: 8035141
    Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu
  • Patent number: 8035111
    Abstract: Monolithic electronic devices are providing including a high bandgap layer. A first type of nitride device is provided on a first portion of the high bandgap layer, the first nitride device including first and second implanted regions respectively defining source and drain regions of the first type of nitride device. A second type of nitride device, different from the first type of nitride device, is provided on a second portion of the high bandgap layer, the second type of nitride device including an implanted highly conductive region. At least a portion of the implanted highly conductive region of the second type of nitride device is coplanar with at least a portion of both the first and second implanted regions of the first type of nitride device.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 11, 2011
    Assignee: Cree, Inc.
    Inventor: Scott T. Sheppard
  • Publication number: 20110241083
    Abstract: Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80?) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80?) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801?, 801-1, 801-2, 801-3) conveniently provides this switching function.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vishnu K. Khemka, Tahir A. Khan, Weixiao Huang, Ronghua Zhu
  • Patent number: 8017045
    Abstract: Provided is a composition for an oxide semiconductor thin film and a field effect transistor (FET) using the composition. The composition includes from about 50 to about 99 mol % of a zinc oxide (ZnO); from about 0.5 to 49.5 mol % of a tin oxide (SnOx); and remaining molar percentage of an aluminum oxide (AlOx). The thin film formed of the composition remains in amorphous phase at a temperature of 400° C. or less. The FET includes an active layer formed of the composition and has improved electrical characteristics. The FET can be fabricated using a low-temperature process without expensive raw materials, such as In and Ga.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: September 13, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Doo Hee Cho, Shin Hyuk Yang, Chun Won Byun, Chi Sun Hwang, Hye Yong Chu, Kyoung Ik Cho
  • Publication number: 20110212584
    Abstract: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.
    Type: Application
    Filed: February 3, 2009
    Publication date: September 1, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, P. R. Chidambaram