Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

Abstract: Transistors having reduced parasitics and enhanced performance. In some embodiments, a transistor can include a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain. The transistor can further include a body configured to provide the conductive channel upon the application of the voltage to the gate. The body can be implemented as a second type active region that butts with the first type active region on the source side at a respective area not covered by the gate, and does not butt with the first type active region on the drain side at a respective area not covered by the gate.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a logic region and a peripheral region; forming initial fins on the semiconductor substrate; forming a protective layer on the sidewall surfaces of the initial fin in the peripheral region; removing the initial fin in the peripheral region to form a trench with a bottom surface lower than a top surface of the isolation structure; forming a modified fin made of a single material in the trench; removing the protective layer; forming a first gate structure having a first gate dielectric layer and surrounding the first fin layers in the logic region across the initial fin in the logic region; and forming a second gate structure having a second gate dielectric layer with a thickness greater than a thickness of the first gate dielectric layer across the modified fins.

Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.

Abstract: The invention provides a flash memory device having flame resistant, which comprises a first shell, a first circuit board, and a first transmission interface. The first circuit board comprises a controller and a plurality of flash memory elements, is disposed within the first shell, and is covered by a fire protection material. The first transmission interface is disposed outside the first shell. A circuit connection line is connected between the first circuit board and the first transmission interface. By the flash memory elements being accommodated within the fire resistant shell, the fire resistant shell will be for isolating high temperature to avoid the flash memory elements to be burned when the flash memory device exists in a fire scene.

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

Abstract: A semiconductor device includes a mesh-patterned power source wiring that supplies respective circuits with a power source voltage supplied to a plurality of locations at an outer periphery of the semiconductor device. The semiconductor device also includes a back-biasing wiring supplying, to a semiconductor substrate, a substrate voltage that controls a threshold voltage of a semiconductor element. The back-biasing wiring includes a upper layer mesh wiring that receives a supply of a substrate voltage, and a lower layer mesh wiring that is provided in a different wiring layer from the upper layer mesh wiring. The outer peripheries of the upper layer mesh wiring and the lower layer mesh wiring are connected to each other through plural vias.

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Abstract: A MISFET has a threshold voltage that is not undesirably increased due to channel narrowing of the MISFET, and the MISFET is reduced in size and increased in withstand voltage. An anti-inversion p-type channel stopper region provided below an element isolation trench has an end that projects toward a channel region below a gate oxide film, and terminates short of the channel region. That is, the end is offset from the end of the channel region (the end of the element isolation trench). This suppresses diffusion in a lateral direction (channel region direction) of an impurity in the p-type channel stopper region, and thus suppresses a decrease in carrier concentration at the end of the channel region. As a result, a local increase in threshold voltage is suppressed.

Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

Abstract: A method for forming a semiconductor device is provided. First, a dielectric layer is provided on a substrate, wherein a first recess and a second recess are formed in the dielectric layer. After a mask layer is filled into the first recess and the second recess, the mask layer in the second recess is removed away, thereby forming a patterned mask layer. Subsequently, a nitride treatment is performed to remove unwanted residue of the mask layer in the second recess.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate; forming a thermal oxide layer on the substrate and the doped region; removing the thermal oxide layer to form a first recess; forming an epitaxial layer on the substrate and in the first recess; and forming a gate dielectric layer in the epitaxial layer.

Abstract: An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.

Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.

Abstract: A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

Abstract: A semiconductor device includes a substrate having a first active region, a first gate structure over the first active region, wherein the first gate structure includes a first interfacial layer having a convex top surface, a first high-k dielectric over the first interfacial layer, and a first gate electrode over the first high-k dielectric.

Abstract: A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.

Abstract: It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: {[N]—[H]}/2?1.0×1021 cm?3.

Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

Abstract: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: A thin film transistor array substrate includes a substrate, a gate line and a data line arranged to cross each other and to define a pixel region on the substrate, a first common line disposed to be parallel to the gate line and to cross the data line, a switch element disposed at an intersection of the gate line and data line, a first pixel electrode formed to overlap the first common line, and a second pixel electrode branched from the first pixel electrode in a plurality of strips, a second common line opposite to the first common line in the center of the pixel region, a second common electrode branched from the second common line toward the pixel region into a plurality of strips, and a third common electrode branched to overlap the data line from the second common line, and a first storage electrode branched from the first common line into the pixel region, and a second storage electrode extended to overlap the first storage electrode from the first pixel electrode.

Abstract: An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location. Deposition of the dummy gate polysilicon layer fills the trench with polysilicon; the resistor polysilicon portion is protected from dummy gate polysilicon removal by a hard mask layer. The resistor polysilicon can be doped during source/drain implant, and can have its contact locations silicide-clad without degrading the metal gate electrode.

Abstract: A thin film transistor array substrate including a substrate, a gate line intersecting a data line to define a pixel region on the substrate, a switching element disposed at an intersection of the gate line and the data line, a plurality of pixel electrodes and a plurality of first common electrodes alternately arranged on a protective film in the pixel region, a second common electrode overlapping the data line, a first storage electrode on the substrate, a second storage electrode overlapping the first storage electrode, and an organic insulation film on the switching element, the second storage electrode, the data line, a gate pad, and a data pad, wherein the second common electrode covers the data line, the protective film and the organic insulation film, and has inclined surfaces connected to the protective film within the pixel region.

Abstract: A system and a method for transistor level routing are disclosed. The method comprises forming a high-k dielectric layer over a substrate, forming a metal layer directly over the high-k dielectric layer, and selectively disposing a semiconductive layer over the metal layer. The method further comprises forming a first transistor in a first region and a second transistor in a second region spaced from the first region, the first and second transistor having gate stacks comprising a high-k dielectric layer, a metal layer and a semiconductive layer, and forming an electrical connection between the first transistor and the second transistor comprising the high-k dielectric layer and the metal layer but not the semiconductive layer.

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

Abstract: A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.

Abstract: Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract: A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.

Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

Abstract: A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.

Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.

Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.

Abstract: An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers.

Abstract: A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Abstract: Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.

Abstract: Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Abstract: A semiconductor device includes a substrate, a semiconductor, a first surface passivation film including nitride, a second passivation film, a gate electrode, and a source electrode and a drain electrode. The semiconductor layer is provided on the substrate. The first surface passivation film including nitride is provided on the semiconductor layer and has at least two openings. The second surface passivation film covers an upper surface and a side surface of the first surface passivation film. The gate electrode is provided on a part of the second surface passivation film. The source electrode and the drain electrode are respectively provided on the two openings. In addition, the second surface passivation film includes a material of which melting point is higher than the melting points of the gate electrode, the source electrode, and the drain electrode.