Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height.

Abstract: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

Abstract: A method of manufacturing an MIS semiconductor device includes forming a high dielectric film on a main surface of a semiconductor substrate, forming a silicon film on the high dielectric film, annealing the semiconductor substrate after the silicon film is formed, processing the high dielectric film and the silicon film into a gate pattern after the semiconductor substrate is annealed, to form a gate insulating film and a gate electrode, and forming source and drain regions on the main surface of the semiconductor substrate using the gate electrode as a mask.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiOx?2, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.

Abstract: Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and t

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.