With Particular Manufacturing Method Of Wells Or Tubs, E.g., Twin Tubs, High Energy Well Implants, Buried Implanted Layers For Lateral Isolation (billi) (epo) Patents (Class 257/E21.63)
  • Patent number: 11495503
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11031073
    Abstract: A Static Random Access Memory (SRAM) cell includes a first boundary and a second boundary opposite to, and parallel to, the first boundary, a first and a second pull-up transistor, a first and a second pull-down transistor forming cross-latched inverters with the first and the second pull-up transistors, and a first and a second pass-gate transistor. Each of the first and the second pull-up transistors, the first and the second pull-down transistors, and the first and the second pass-gate transistors includes a bottom plate as a first source/drain region, a channel over the bottom plate, and a top plate over the channel as a second source/drain region. The SRAM cell further includes a first, a second, a third, and a fourth active region, each extending from the first boundary to the second boundary.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10672644
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 2, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Franck Julien
  • Patent number: 9899272
    Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Poren Tang, Sunjung Steve Kim, Moon Seung Yang, Seung Hun Lee, Hyun Jung Lee, Geun Hee Jeong
  • Patent number: 9871113
    Abstract: A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 16, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Wei Yu, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 9508588
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Carsten Grass, Martin Trentzsch, Sören Jansen
  • Patent number: 8994026
    Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8963158
    Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8946859
    Abstract: An integrated circuit chip including a plurality of parallel wells of alternated conductivity types formed in the upper portion of a semiconductor substrate of a first conductivity type, and a device of protection against attacks including: between the wells, trenches with insulated walls filled with a conductive material, said trenches extending from the upper surface of the wells to the substrate; and a circuit capable of detecting a modification of the stray capacitance formed between said conductive material and a region of the chip.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 3, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Mathieu Lisart, Alexandre Sarafianos
  • Patent number: 8841180
    Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack T. Kavalieros, Been-Yih Jin
  • Patent number: 8815698
    Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 26, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8614128
    Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 24, 2013
    Assignee: Suvolta, Inc.
    Inventors: Scott E. Thompson, Thomas Hoffmann, Lance Scudder, U. C. Sridharan, Dalong Zhao, Pushkar Ranade, Michael Duane, Paul E. Gregory
  • Patent number: 8519402
    Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8455338
    Abstract: A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: June 4, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiya Nakamori
  • Patent number: 8320165
    Abstract: An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 27, 2012
    Assignee: Texas Instrument Incorporated
    Inventors: Robert R. Garcia, Theodore W. Houston
  • Patent number: 8315086
    Abstract: An integrated circuit containing an SRAM array having a strap row and an SRAM cell row. The strap row includes a tap connecting region that connects two columnar regions of a first polarity well. The strap row also includes a well tap active area in a tap connecting well region. The well tap active area includes a tap layer and a well contact plug that is disposed on the top surface of the tap layer.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 8310860
    Abstract: An integrated circuit containing an SRAM array having a strap row. The strap row has a well tap active area that partially overlaps adjacent first polarity wells and a second polarity well that is located between the adjacent first polarity wells. A well contact plug is disposed on a top surface of a tap layer located within the well tap active area.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Publication number: 20120175699
    Abstract: A power semiconductor device having a self-aligned structure and super pinch-off regions is disclosed. The on-resistance is reduced by forming a short channel without having punch-through issue. The on-resistance is further reduced by forming an on-resistance reduction implanted drift region between adjacent shield electrodes, having doping concentration heavier than epitaxial layer without degrading breakdown voltage with a thick oxide on bottom and sidewalls of the shield electrode. Furthermore, the present invention enhance the switching speed comparing to the prior art.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: FORCE MOS TECHNOLOGY CO., LTD.
    Inventor: Fu-Yuan HSIEH
  • Publication number: 20120178211
    Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Francois Hebert
  • Publication number: 20120153401
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.
    Type: Application
    Filed: August 3, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter JAVORKA, Maciej WIATR, Stephan-Detlef KRONHOLZ
  • Patent number: 8198150
    Abstract: A low thermal pathway is provided from the top surface of a silicon substrate to the bottom surface of the silicon substrate by first forming aluminum plugs in the bottom surface of the silicon substrate that contact the silicon substrate and extend up towards the top surface, and then heating the aluminum plugs to a temperature for a period of time sufficient to cause spikes to grow from the sides of the aluminum plugs.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: June 12, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Visvamohan Yegnashankaran
  • Patent number: 8125041
    Abstract: A semiconductor device includes: a semiconductor substrate 1; a through electrode 7 extending through the semiconductor substrate 1; a diffusion layer 24 formed in a region of an upper portion of the semiconductor substrate 1 located on a side of the through electrode 7; and a diffusion layer 22 formed in an upper portion of the diffusion layer 24. A portion of the side surface of the through electrode 7 facing the diffusion layer 24 is curved, and a portion of the surface of the diffusion layer 24 facing the through electrode 7 is curved.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: February 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Kyoko Fujii
  • Publication number: 20120001655
    Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.
    Type: Application
    Filed: April 28, 2011
    Publication date: January 5, 2012
    Applicant: STMicroelectronics S.r.I.
    Inventors: Luca CICCARELLI, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Valentina Nardone
  • Patent number: 8039326
    Abstract: Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andreas Knorr, Frank Scott Johnson
  • Patent number: 7977200
    Abstract: A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Stephen E. Luce
  • Patent number: 7964894
    Abstract: An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: June 21, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
  • Patent number: 7943461
    Abstract: A high-voltage semiconductor device and a method for manufacturing the same are disclosed. The disclosed high-voltage semiconductor device includes a semiconductor substrate, a first N type well in the semiconductor substrate, a first P type well in the first N type well, second N type wells in the first N type well along a periphery of the first P type well, a gate insulating film and a gate electrode on the first P type well, and first heavily-doped N type impurity regions in the first P type well at opposite sides of the gate electrode.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: May 17, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Duck Ki Jang
  • Patent number: 7915688
    Abstract: A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi
  • Patent number: 7906389
    Abstract: A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 15, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 7855116
    Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: December 21, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Kiyotoshi
  • Publication number: 20100297837
    Abstract: A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate.
    Type: Application
    Filed: May 21, 2009
    Publication date: November 25, 2010
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Publication number: 20100289082
    Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate.
    Type: Application
    Filed: May 12, 2009
    Publication date: November 18, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. Adkisson, Andres Bryant, Mark D. Jaffe, Alain Loiseau
  • Patent number: 7776643
    Abstract: A solid state image pickup device is provided which includes: charge accumulation regions disposed in a semiconductor substrate in a matrix shape; a plurality of vertical transfer channels formed in the semiconductor substrate each in a close proximity to each column of the charge accumulation regions; vertical transfer electrodes formed above the vertical transfer channels; a channel protective impurity layer formed just under the vertical transfer channel and surrounding the charge accumulation region; one or more pixel separation impurity layers formed under the channel protective impurity layer and at a position facing the channel protective impurity layer; an overflow barrier region having a peak position of an impurity concentration at a position deeper than the pixel separation impurity layer, the peak position of the impurity concentration being at a depth of 3 ?m or deeper from a surface of the semiconductor substrate; and a horizontal CCD for transferring signal charges transferred from the vertical
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: August 17, 2010
    Assignee: Fujifilm Corporation
    Inventors: Yuko Nomura, Shinji Uya
  • Patent number: 7772647
    Abstract: Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7755146
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 13, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Mark Helm, Xianfeng Zhou
  • Patent number: 7736957
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 15, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Darren V. Goedeke, Voon-Yew Thean, Stefan Zollner
  • Patent number: 7714358
    Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Shreesh Narasimha, Katsunori Onishi, Kern Rim
  • Patent number: 7700470
    Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Uday Shah, Jack T. Kavalieros, Brian S. Doyle
  • Patent number: 7696579
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: April 13, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mark Helm, Xianfeng Zhou
  • Patent number: 7691734
    Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Patent number: 7691701
    Abstract: Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: April 6, 2010
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc.
    Inventors: Michael P. Belyansky, Siddarth A. Krishnan, Unoh Kwon, Naim Moumen, Ravikumar Ramachandran, James Kenyon Schaeffer, Richard Wise, Keith Kwong Hon Wong, Hongwen Yan
  • Patent number: 7687363
    Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region; forming a gate electrode on the semiconductor substrate; and implanting impurity ions using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Choul Joo Ko
  • Patent number: 7682918
    Abstract: A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 23, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Alvin Sugerman, Steven Park
  • Patent number: 7659157
    Abstract: A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Greene, Mahender Kumar
  • Patent number: 7645658
    Abstract: A method of manufacturing a silicon carbide semiconductor device having a MOS structure includes preparing a substrate made of silicon carbide, and forming a channel region, a first impurity region, a second impurity region, a gate insulation layer, and a gate electrode to form a semiconductor element on the substrate. In addition, a film is formed on the semiconductor element to provide a material of an interlayer insulation layer, and a reflow process is performed at a temperature about 700° C. or over in an wet atmosphere so that the interlayer insulation layer is formed from the film. Furthermore, a dehydration process is performed at about 700° C. or lower in an inert gas atmosphere after the reflow process is performed.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 12, 2010
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Nakamura, Hiroyuki Ichikawa, Eiichi Okuno
  • Patent number: 7632724
    Abstract: A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: December 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, William K. Henson, Yaocheng Liu
  • Patent number: 7612422
    Abstract: Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Luigi Colombo, Mark Robert Visokay
  • Patent number: 7608501
    Abstract: By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device having different types of transistors may be provided, in which a high degree of metal silicide integrity as well as a highly efficient stress transfer mechanism is achieved.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: October 27, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Carsten Peters, Matthias Schaller, Heike Salz
  • Patent number: 7605412
    Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 20, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
  • Patent number: RE42776
    Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: October 4, 2011
    Assignee: Marvell International Ltd.
    Inventors: Lawrence T. Clark, Vikas R. Amrelia, Raphael A. Soetan, Eric J. Hoffman, Tuan X. Do